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Add the BSP for SensorTile.box board with documentation.
And a sample code to test it out.

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zephyrbot commented Aug 12, 2019

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@erwango erwango added the platform: STM32 ST Micro STM32 label Aug 12, 2019
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@dbkinder
Thx! Applied all ur suggestions, re-based to latest master and re-pushed!

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one typo, otherwise LGTM

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@dbkinder
Fixed and rebased

@avisconti avisconti added this to the v2.1.0 milestone Sep 3, 2019
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I rebased this PR on top of #19068.

@dbkinder is now the doc fine?

@erwango @MaureenHelm
Any thoughts on this PR?

@zephyrbot zephyrbot added area: Sensors Sensors area: Tests Issues related to a particular existing or missing test labels Sep 11, 2019
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Few comments otherwise is good and clean

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STM32FL4Rx

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Since you provided the dfu-runner info, I guess that usual west flash command will work.
It would be good adding and example of west flash/debug commands for zephyr beginners.

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_NSS pins should be defined under

#ifdef CONFIG_SPI_STM32_USE_HW_SS

Introduced in #17806

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Ditto

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ditto

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Comment not in line with configuration, or misleading.

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LGTM, thanks for the doc updates!

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@erwango
Thanks for the review. I will implement step by step as soon as possible.
I have a request for you and I may probably open an official request. The SensorTile.box
is using the STM32L4R9 SoC, but currently only STM32L4R5 is handled in zephyr, so I stick
on this one for the moment. Do you have plan to address it?

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erwango commented Sep 12, 2019

@avisconti, no issue with adding STM32L4R9. It could actually be done in the current PR, which will be used as validation. From what I see STM32L4R9 is a direct superset of STM32L4R5, so addition should be minor:

  • update soc/arm/st_stm32/stm32l4/Kconfig.soc with new reference
  • add soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r9xx file
  • add dts/arm/st/l4/stm32l4r9.dtsi as a superset of dts/arm/st/l4/stm32l4r5.dtsi
  • add dts/arm/st/l4/stm32l4r9X?.dtsi defining the soc memory attributes.

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@avisconti, no issue with adding STM32L4R9. It could actually be done in the current PR, which will be used as validation. From what I see STM32L4R9 is a direct superset of STM32L4R5, so addition should be minor:

  • update soc/arm/st_stm32/stm32l4/Kconfig.soc with new reference
  • add soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r9xx file
  • add dts/arm/st/l4/stm32l4r9.dtsi as a superset of dts/arm/st/l4/stm32l4r5.dtsi
  • add dts/arm/st/l4/stm32l4r9X?.dtsi defining the soc memory attributes.

@erwango
OK, next week I'll take a look at it. I may need your help though.

@avisconti avisconti force-pushed the add-stile-box branch 2 times, most recently from 3c34e36 to 21dcf98 Compare September 16, 2019 09:39
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@avisconti, no issue with adding STM32L4R9. It could actually be done in the current PR, which will be used as validation. From what I see STM32L4R9 is a direct superset of STM32L4R5, so addition should be minor:

  • update soc/arm/st_stm32/stm32l4/Kconfig.soc with new reference
  • add soc/arm/st_stm32/stm32l4/Kconfig.defconfig.stm32l4r9xx file
  • add dts/arm/st/l4/stm32l4r9.dtsi as a superset of dts/arm/st/l4/stm32l4r5.dtsi
  • add dts/arm/st/l4/stm32l4r9X?.dtsi defining the soc memory attributes.

@erwango
OK, next week I'll take a look at it. I may need your help though.

@erwango,

I re-pushed it.
Now I added support for STM32L4R9 SoC. It is just an easy modification, so it would require some attention/suggestions from your side.

@avisconti avisconti requested a review from erwango September 16, 2019 16:06
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@erwango
stm32l4r9.dtsi now only includes stm32l4r5.dtsi, that's all.
I think this was your intention.

Concerning flash size, is it same as stm32l4r5? I didn't check it to be honest...

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erwango commented Sep 18, 2019

@avisconti, You're using "zi" ("Xi") variant so, it should be the same.

The correct suffix name for selecting the GPIO for SPI Chip Select
is _CS_GPIOS_CONTROLLER and not _CS_GPIO_CONTROLLER.

Signed-off-by: Armando Visconti <[email protected]>
Add support for ST stm32l4r9xx System-on-Chip.

See http://www.st.com/en/microcontrollers/stm32l4r9-s9.html
for more details.

Signed-off-by: Armando Visconti <[email protected]>
This commit adds:

 1. pin definitions for SPI1 on PE12-15 on STM32L4 devices
 2. SPI3 on PA15_SPI3_NSS

Signed-off-by: Armando Visconti <[email protected]>
The SensorTile.box is a board designed for IoT applications
embedding a wide range of intelligent low power MEMS sensors,
a STM32L4 microcontroller to manage sensor configuration and
process sensor output data, a micro-USB battery charging
interface and an ST Bluetooth Low Energy module for wireless
communication with a BLE-enabled smartphone.

Signed-off-by: Armando Visconti <[email protected]>
Add sample to test SensorTile.box board.

Signed-off-by: Armando Visconti <[email protected]>
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avisconti commented Sep 18, 2019

@dbkinder

Since IIS3DHHC driver has been recently merged (#19042) I decided to add to sample code also the test for it. And I have changed the sample documentation.

@erwango @galak

While testing IIS3DHHC for this board (is on SPI bus) I realize that there was some typos on CS_GPIO DT name. So I fixed it and put the fix in this PR (ebbdc8a)

@avisconti avisconti requested a review from dbkinder September 18, 2019 13:48
@galak galak merged commit af0e2c5 into zephyrproject-rtos:master Sep 19, 2019
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