[AArch64] Removed redundant FMOV instruction for truncstores of f64/f32 via bitcast to i64/i32/i8.

[Amichaxx]

Previously, storing the low bits of a double, which was bitcast to i64 and truncated to i32 or i16, would emit a redundant FMOV. This patch introduces new TableGen patterns to avoid the unnecessary FMOV. Tests added: bitcast_truncstore.ll

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[llvmbot]

@llvm/pr-subscribers-backend-aarch64

Author: Amina Chabane (Amichaxx)

Changes

Previously, storing the low bits of a double, which was bitcast to i64 and truncated to i32 or i16, would emit a redundant FMOV. This patch introduces new TableGen patterns to avoid the unnecessary FMOV. Tests added: bitcast_truncstore.ll

---

Full diff: https://github.com/llvm/llvm-project/pull/149997.diff

2 Files Affected:

• (modified) llvm/lib/Target/AArch64/AArch64InstrInfo.td (+8)
• (added) llvm/test/CodeGen/AArch64/bitcast_truncstore.ll (+26)

diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
index 0cb7b02d84a6e..aa635b188da70 100644
--- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td
+++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td
@@ -4649,6 +4649,14 @@ let Predicates = [IsLE] in {
             (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
 }
 
+// truncstorei32 of f64 bitcasted to i64
+def : Pat<(truncstorei32 (i64 (bitconvert (f64 FPR64:$Rt))), (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
+          (STRSui (EXTRACT_SUBREG FPR64:$Rt, ssub), GPR64sp:$Rn, uimm12s4:$offset)>;
+
+// truncstorei16 of f64 bitcasted to i64
+def : Pat<(truncstorei16 (i64 (bitconvert (f64 FPR64:$Rt))), (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
+          (STRHui (f16 (EXTRACT_SUBREG FPR64:$Rt, hsub)), GPR64sp:$Rn, uimm12s2:$offset)>;     
+
 // truncstore i64
 def : Pat<(truncstorei32 GPR64:$Rt,
                          (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
diff --git a/llvm/test/CodeGen/AArch64/bitcast_truncstore.ll b/llvm/test/CodeGen/AArch64/bitcast_truncstore.ll
new file mode 100644
index 0000000000000..8e0d0c2158090
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/bitcast_truncstore.ll
@@ -0,0 +1,26 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
+
+define void @_Z10store_i64_from_f64Pjd(ptr %n, double noundef %x){
+; CHECK-LABEL: _Z10store_i64_from_f64Pjd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    str s0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %0 = bitcast double %x to i64
+  %conv = trunc i64 %0 to i32
+  store i32 %conv, ptr %n, align 4
+  ret void
+}
+
+define void @_Z9store_i16Ptd(ptr %n, double noundef %x) {
+; CHECK-LABEL: _Z9store_i16Ptd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    str h0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %0 = bitcast double %x to i64
+  %conv = trunc i64 %0 to i16
+  store i16 %conv, ptr %n, align 2
+  ret void
+}

[davemgreen]

Can we add patterns and tests for the other types, similar to #146920?

[CarolineConcatto]

Thank you Amina,

[CarolineConcatto]

Thank you Amina,
The patch looks good.
Can you align the stores before merging the patch please.

[Amichaxx]

@davemgreen Hi, just wondering if the changes look okay to you? Thanks.

[davemgreen]

Yep, LGTM. Do you want me to hit submit?

[Amichaxx]

Yes please :)

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