[AArch64] Add TableGen patterns for truncstore of bitcasted FP values (f64/f32 → i32/i16/i8X)

Author: Amichaxx

llvm/lib/Target/AArch64/AArch64InstrInfo.td

@@ -4706,6 +4706,30 @@ let Predicates = [IsLE] in {
             (STRQui FPR128:$Rt, GPR64sp:$Rn, uimm12s16:$offset)>;
 }
 
+// truncstorei32 of f64 bitcasted to i64
+def : Pat<(truncstorei32 (i64 (bitconvert (f64 FPR64:$Rt))), (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),
+          (STRSui (EXTRACT_SUBREG FPR64:$Rt, ssub), GPR64sp:$Rn, uimm12s4:$offset)>;
+
+// truncstorei16 of f64 bitcasted to i64
+def : Pat<(truncstorei16 (i64 (bitconvert (f64 FPR64:$Rt))), (am_indexed16 GPR64sp:$Rn, uimm12s2:$offset)),
+          (STRHui (f16 (EXTRACT_SUBREG FPR64:$Rt, hsub)), GPR64sp:$Rn, uimm12s2:$offset)>;      
+
+let Predicates = [HasFullFP16] in {
+  // truncstorei16 of f32 bitcasted to i32
+  def : Pat<(truncstorei16 (i32 (bitconvert (f32 FPR32:$Rt))), (am_indexed16 GPR64sp:$Rn, uimm12s2:$off)),
+          (STRHui (f16 (EXTRACT_SUBREG FPR32:$Rt, hsub)), GPR64sp:$Rn, uimm12s2:$off)>;
+}
+
+let Predicates = [HasFPARMv8] in {
+  // truncstorei8 of f64 bitcasted to i64
+  def : Pat<(truncstorei8 (i64 (bitconvert (f64 FPR64:$Rt))), (am_indexed8 GPR64sp:$Rn, uimm12s1:$off)),
+          (STRBui (aarch64mfp8 (EXTRACT_SUBREG FPR64:$Rt, bsub)), GPR64sp:$Rn, uimm12s1:$off)>;
+
+  // truncstorei8 of f32 bitcasted to i32
+  def : Pat<(truncstorei8 (i32 (bitconvert (f32 FPR32:$Rt))), (am_indexed8 GPR64sp:$Rn, uimm12s1:$off)),
+        (STRBui (aarch64mfp8 (EXTRACT_SUBREG FPR32:$Rt, bsub)), GPR64sp:$Rn, uimm12s1:$off)>;
+}
+
 // truncstore i64
 def : Pat<(truncstorei32 GPR64:$Rt,
                          (am_indexed32 GPR64sp:$Rn, uimm12s4:$offset)),

llvm/test/CodeGen/AArch64/bitcast_truncstore.ll

@@ -0,0 +1,60 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
+; RUN: llc -mtriple=aarch64-unknown-linux-gnu -mattr=+fp-armv8,+fullfp16 < %s | FileCheck %s
+
+
+define void @_Z10store_f64i32Pjd(ptr %n, double noundef %x){
+; CHECK-LABEL: _Z10store_f64i32Pjd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    str s0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %0 = bitcast double %x to i64
+  %conv = trunc i64 %0 to i32
+  store i32 %conv, ptr %n, align 4
+  ret void
+}
+
+define void @_Z9store_f64i16Ptd(ptr %n, double noundef %x){
+; CHECK-LABEL: _Z9store_f64i16Ptd:
+; CHECK:       // %bb.0: // %entry
+; CHECK-NEXT:    str h0, [x0]
+; CHECK-NEXT:    ret
+entry:
+  %0 = bitcast double %x to i64
+  %conv = trunc i64 %0 to i16
+  store i16 %conv, ptr %n, align 2
+  ret void
+}
+
+define void @_Z13store_f64i8Phd(ptr %0, double noundef %1){
+; CHECK-LABEL: _Z13store_f64i8Phd:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    str b0, [x0]
+; CHECK-NEXT:    ret
+  %3 = bitcast double %1 to i64
+  %4 = trunc i64 %3 to i8
+  store i8 %4, ptr %0, align 1
+  ret void
+}
+
+define void @_Z17store_f32i16Ptf(ptr %0, float noundef %1){
+; CHECK-LABEL: _Z17store_f32i16Ptf:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    str h0, [x0]
+; CHECK-NEXT:    ret
+  %3 = bitcast float %1 to i32
+  %4 = trunc i32 %3 to i16
+  store i16 %4, ptr %0, align 2
+  ret void
+}
+
+define void @_Z16store_f32i8Phf(ptr  %0, float noundef %1){
+; CHECK-LABEL: _Z16store_f32i8Phf:
+; CHECK:       // %bb.0:
+; CHECK-NEXT:    str b0, [x0]
+; CHECK-NEXT:    ret
+  %3 = bitcast float %1 to i32
+  %4 = trunc i32 %3 to i8
+  store i8 %4, ptr %0, align 1
+  ret void
+}