drivers: clock_control: introduce bl60x clock control

[VynDragon]

This introduces clock control for bl60x.

Reason for kconfig.bflb: other soc will also be in there:

# Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
# SPDX-License-Identifier: Apache-2.0

config CLOCK_CONTROL_BOUFFALOLAB_BL61X
	bool "Bouffalolab BL61x Clock Control Driver"
	default y
	depends on DT_HAS_BFLB_BL61X_CLOCK_CONTROLLER_ENABLED

config CLOCK_CONTROL_BOUFFALOLAB_BL60X
	bool "Bouffalolab BL60x Clock Control Driver"
	default y
	depends on DT_HAS_BFLB_BL60X_CLOCK_CONTROLLER_ENABLED

config CLOCK_CONTROL_BOUFFALOLAB_BL70X
	bool "Bouffalolab BL70x Clock Control Driver"
	default y
	depends on DT_HAS_BFLB_BL70X_CLOCK_CONTROLLER_ENABLED

Reason for deferred: sadly couldnt make it work in the hybrid version due to conflict between SDK init and zephyr init, this is to avoid submitting removing dependency to SDK and this at the same time and be a really big PR.

Some of the updates to other things (like syscon) will come later.

[ycsin]

o.O this looks familiar to the other PR

[VynDragon]

Same code. Still havent figured how to share it well between the drivers. force temporary 32m sysclk with on and off, or maybe a function like irq_lock, idk.

[ycsin]

Hmm.. maybe create a header file in include/zephyr/drivers/clock_control for these functions so that it can be reused in other drivers like the recently added syscon?

[VynDragon]

Ok, i will make a separate commit for that later to update both this and the syscon driver.

[Copilot]

Pull Request Overview

This PR adds Bouffalolab BL60x clock control, including device tree bindings, Kconfig entries, and driver registration.

• Enable CLOCK_CONTROL for BL60x SoC and add Kconfig entry for the BL60x clock driver
• Introduce common and BL60x-specific dt-bindings headers and YAML files
• Update the BL60x device tree (dtsi) and register the new driver in CMakeLists

Reviewed Changes

Copilot reviewed 13 out of 13 changed files in this pull request and generated 2 comments.

Show a summary per file

File	Description
soc/bflb/bl60x/Kconfig	Select CLOCK_CONTROL for BL60x SoC
include/zephyr/dt-bindings/clock/bflb_clock_common.h	New common clock ID definitions and frequency macro
include/zephyr/dt-bindings/clock/bflb_bl60x_clock.h	BL60x-specific clock ID mappings
dts/riscv/bflb/bl60x.dtsi	Add fixed-clock nodes and clock-controller node
dts/bindings/clock/*.yaml	New YAML bindings for controller, root, PLL, and BCLK
drivers/clock_control/Kconfig.bflb	Add CLOCK_CONTROL_BOUFFALOLAB_BL60X config
drivers/clock_control/Kconfig	Source the new BL60x Kconfig.bflb file
drivers/clock_control/CMakeLists.txt	Register clock_control_bl60x.c under the new config

Comments suppressed due to low confidence (6)

dts/riscv/bflb/bl60x.dtsi:3

• There are now two differing copyright headers in this file; please consolidate into a single, correct line covering both the original ATL Electronics and the new MASSDRIVER ownership.

* Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space)

dts/bindings/clock/bflb,bl60x-pll.yaml:20

• [nitpick] The clock-cells entry 'select' is ambiguous; consider renaming it to something more descriptive (e.g., 'pll-rate' or 'output-index').

  - select

drivers/clock_control/CMakeLists.txt:57

• No tests for the new BL60x clock controller are included; consider adding a basic unit or integration test under tests/drivers/clock_control to verify proper initialization and behavior.

zephyr_library_sources_ifdef(CONFIG_CLOCK_CONTROL_BOUFFALOLAB_BL60X   clock_control_bl60x.c)

include/zephyr/dt-bindings/clock/bflb_clock_common.h:18

• The MHZ macro may not be defined in this header. Consider including the common DT macros header (e.g., <zephyr/dt-bindings/dt-common.h>) or using an explicit frequency literal.

#define BFLB_RC32M_FREQUENCY MHZ(32)

include/zephyr/dt-bindings/clock/bflb_bl60x_clock.h:18

• [nitpick] Found mixed tabs and spaces in indentation for the PLL definitions; please use spaces consistently to match the repository style.

#define BL60X_PLL_48MHz		0

dts/riscv/bflb/bl60x.dtsi:131

• [nitpick] Entries in the phandle list wrap mid-sentence and indentation is inconsistent; align the list items vertically for better readability.

clocks = <&clk_rc32m>, <&clk_crystal>, <&clk_root>, <&clk_bclk>,

[ycsin]

I find only writing to the return value when important

It is kinda important here - we tried to handle the input and we can't, so the input is invalid and we set the return value accordingly

[ycsin]

some nits, LGTM in general. Hopefully later PRs will factor out some common code that can be reused between drivers.

[ycsin]

nits: I think it's better to set ret = -EINVAL; in the else case here and clock_control_bl60x_off()

[VynDragon]

The default negative logic will stay.

[kartben]

function returns an unsigned int...

[VynDragon]

Should be unreacheable code anyway, done.

[kartben]

function returns a clock_control_status - I think you want CLOCK_CONTROL_STATUS_UNKNOWN?

[VynDragon]

Introduced by review... Done.

addressed - thanks!

[sonarqubecloud]

Quality Gate passed

Issues
3 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

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