soc: bflb: enable clock_control for bl60x

This enables the clock_control driver build on bl60x.
It is currently deferred init, due to being incompatible
with current SDK-based boot, to avoid later giant PR.

Signed-off-by: Camille BAUD <[email protected]>

Author: VynDragon

dts/riscv/bflb/bl60x.dtsi

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2021-2025 ATL Electronics
+ * Copyright (c) 2024-2025 MASSDRIVER EI (massdriver.space)
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -13,6 +14,44 @@
 	#address-cells = <1>;
 	#size-cells = <1>;
 
+	clocks {
+		clk_rc32m: clk-rc32m {
+			#clock-cells = <0>;
+			compatible = "bflb,rc32m";
+			status = "okay";
+		};
+
+		clk_crystal: clk-crystal {
+			#clock-cells = <0>;
+			compatible = "bflb,crystal";
+			clock-frequency = <DT_FREQ_M(40)>;
+			status = "okay";
+		};
+
+		clk_pll: clk-pll {
+			#clock-cells = <0>;
+			compatible = "bflb,bl60x-pll";
+			clocks = <&clk_crystal>;
+			status = "okay";
+		};
+
+		clk_root: clk-root {
+			#clock-cells = <0>;
+			compatible = "bflb,bl60x-root-clk";
+			clocks = <&clk_pll>;
+			pll-select = <3>;
+			divider = <1>;
+			status = "okay";
+		};
+
+		clk_bclk: clk-bclk {
+			#clock-cells = <0>;
+			compatible = "bflb,bclk";
+			divider = <2>;
+			status = "okay";
+		};
+	};
+
 	cpus {
 		#address-cells = <1>;
 		#size-cells = <0>;
@@ -83,6 +122,18 @@
 			};
 		};
 
+		clocks: clock-controller@40000000 {
+			compatible = "bflb,bl60x-clock-controller", "bflb,clock-controller";
+			reg = <0x40000000 DT_SIZE_K(4)>;
+			#clock-cells = <1>;
+			status = "okay";
+			clocks = <&clk_rc32m>, <&clk_crystal>, <&clk_pll>,
+				<&clk_root>, <&clk_bclk>;
+			clock-names = "rc32m", "crystal", "pll",
+				"root", "bclk";
+			zephyr,deferred-init;
+		};
+
 		efuse: efuse@40007000 {
 			compatible = "bflb,efuse";
 			reg = <0x40007000 0x1000>;

soc/bflb/bl60x/Kconfig

@@ -4,6 +4,7 @@
 
 config SOC_SERIES_BL60X
 	select ATOMIC_OPERATIONS_C
+	select CLOCK_CONTROL
 	select CPU_HAS_FPU
 	select INCLUDE_RESET_VECTOR
 	select RISCV