add support for configuring LPC clocks using devicetree

boards/arm/lpcxpresso55s69/lpcxpresso55s69-clocks.dtsi

@@ -0,0 +1,54 @@
+/*
+ * Copyright 2023 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/* Configure clock tree for 150Mhz operation */
+&syscon {
+	/* Enable FRO 12m as input for PLL0 */
+	fro-12m {
+		status = "okay";
+	};
+
+	/* PLL0 should clock from FRO12m */
+	pll0clksel {
+		status = "okay";
+		sel = <&fro_12m>;
+		/* Raw PLL0 output frequency of 300MHz */
+		pll0 {
+			status = "okay";
+			mult = <25>;
+			div = <1>;
+			pll0-pdec {
+				status = "okay";
+				div = <2>;
+			};
+		};
+	};
+	/* Route PLL0 output through PDEC, which divides to 150MHz */
+	pll0-directo {
+		status = "okay";
+		sel = <&pll0_pdec>;
+	};
+	pll0-bypass {
+		status = "okay";
+		sel = <&pll0_directo>;
+	};
+	/* Route PLL0 main clock through mainclkselb */
+	mainclkselb {
+		status = "okay";
+		sel = <&pll0_bypass>;
+		/* AHB clk div sets main system clock, which will be 150MHz */
+		ahbclkdiv {
+			status = "okay";
+			div = <1>;
+		};
+	};
+
+	/* Clock Flexcomm0 from FRO12m */
+	fcclksel0 {
+		status = "okay";
+		sel = <&fro_12m>;
+	};
+};

boards/arm/lpcxpresso55s69/lpcxpresso55s69.dtsi

@@ -5,6 +5,7 @@
  */
 
 #include "lpcxpresso55s69-pinctrl.dtsi"
+#include "lpcxpresso55s69-clocks.dtsi"
 
 / {
 	aliases{

boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu0_defconfig

@@ -16,6 +16,7 @@ CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
 CONFIG_ARM_MPU=y
 CONFIG_HW_STACK_PROTECTION=y
 CONFIG_PINCTRL=y
+CONFIG_NXP_DTS_CLOCKING=y
 
 # Enable TrustZone-M
 CONFIG_TRUSTED_EXECUTION_SECURE=y

boards/arm/lpcxpresso55s69/lpcxpresso55s69_cpu1_defconfig

@@ -10,5 +10,6 @@ CONFIG_BOARD_LPCXPRESSO55S69_CPU1=y
 CONFIG_GPIO=y
 CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=96000000
 CONFIG_PINCTRL=y
+CONFIG_NXP_DTS_CLOCKING=y
 
 CONFIG_RUNTIME_NMI=y

drivers/clock_control/clock_control_mcux_syscon.c

@@ -169,8 +169,12 @@ static int mcux_lpc_syscon_clock_control_get_subsys_rate(
 		*rate = CLOCK_GetDcPixelClkFreq();
 		break;
 #endif
+	case MCUX_CORE_CLK:
+		*rate = CLOCK_GetCoreSysClkFreq();
+		break;
 	}
 
+
 	return 0;
 }
 

dts/arm/nxp/nxp_lpc55S6x.dtsi

@@ -26,6 +26,7 @@
 };
 
 #include "nxp_lpc55S6x_common.dtsi"
+#include "nxp_lpc55Sxx_clocks.dtsi"
 
 /*
  * Explicitly enable IAP after we include the common LPC55S6X dtsi file,

dts/arm/nxp/nxp_lpc55S6x_ns.dtsi

@@ -17,3 +17,4 @@
 };
 
 #include "nxp_lpc55S6x_common.dtsi"
+#include "nxp_lpc55Sxx_clocks.dtsi"