add support for configuring LPC clocks using devicetree #62946
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Add generic clock bindings to describe common clock properties for NXP
parts:
clock-gate: simple enable/disable switch for a clock output
clock-mux: clock multiplexor, selects one output from multiple inputs
clock-pll: phase locked loop, multiplies and divides a signal by integer
values
clock-div: divides a clock by integer value.
clock-multiplier: multiplies a clock by integer value.
Signed-off-by: Daniel DeGrasse <[email protected]>
Add devicetree clock definition for LPC55Sxx parts. This clock tree should be valid for the following SOCs: - LPC5526 - LPC5528 - LPC55S26 - LPC55S28 - LPC55S66 - LPC55S69 The clock tree uses the following rules: - all clock roots are defined at the root level - all clock muxes are defined at the root level (since they have multiple parents) - clock divs and gates should be defined under their parent (the clock node they source an input signal from) Signed-off-by: Daniel DeGrasse <[email protected]>
Add code to parse devicetree data to determine clock settings for each mux, div, and clock root on the LPC55xxx series. Currently, only the LPC55S69 is supported using this new clocking scheme, which is opt-in via a Kconfig. Clock settings will only be applied when a given node has status="okay" set at the board level. Signed-off-by: Daniel DeGrasse <[email protected]>
Enable devicetree based clocking by default on the lpcxpresso55s69 targets, as an initial platform to validate this feature on Add board level configuration to clock the core at 150 MHz from PLL0 by default. Signed-off-by: Daniel DeGrasse <[email protected]>
Add MCUX_CORE_CLK identifier, used to get the core system clock at runtime. Signed-off-by: Daniel DeGrasse <[email protected]>
Add tests for NXP devicetree clock configuration. These tests are designed to validate that the SOC can boot from the highest frequency internal oscillator, as well as the highest frequency configuration using an external crystal (typically also the fastest frequency supported by the part) These tests simply validate that the core clock frequency matches what is expected based on the devicetree configuration, by querying the core clock frequency from the clock_control API. Signed-off-by: Daniel DeGrasse <[email protected]>
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This pull request has been marked as stale because it has been open (more than) 60 days with no activity. Remove the stale label or add a comment saying that you would like to have the label removed otherwise this pull request will automatically be closed in 14 days. Note, that you can always re-open a closed pull request at any time. |
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This PR introduces a method of configuring clocks on NXP SOCs using devicetree. The clock tree is encoded using devicetree, and the user is expected to enable and configure clock components at the board level.
This PR contains the following components:
Note- this PR is currently in a draft state, since there is still work to be done to validate the formatting and generation scripts used to create the clock tree at the SOC level.
Signed-off-by: Daniel DeGrasse [email protected]