zephyrproject-rtos · carlescufi · Aug 24, 2023 · Jun 29, 2023 · Jun 29, 2023 · Aug 14, 2023
diff --git a/MAINTAINERS.yml b/MAINTAINERS.yml
@@ -421,7 +421,7 @@ CMSIS-DSP integration:
   collaborators:
     - galak
   files:
-    - modules/Kconfig.cmsis_dsp
+    - modules/cmsis/Kconfig.cmsis_dsp
     - tests/benchmarks/cmsis_dsp/
     - tests/lib/cmsis_dsp/
   labels:
@@ -434,7 +434,7 @@ CMSIS-NN integration:
   collaborators:
     - stephanosio
   files:
-    - modules/Kconfig.cmsis_nn
+    - modules/cmsis/Kconfig.cmsis_nn
     - tests/lib/cmsis_nn/
   labels:
     - "area: CMSIS-NN"
@@ -2854,9 +2854,9 @@ West:
     - microbuilder
     - povergoing
   files:
-    - modules/Kconfig.cmsis
-    - modules/Kconfig.cmsis_dsp
-    - modules/Kconfig.cmsis_nn
+    - modules/cmsis/Kconfig
+    - modules/cmsis/Kconfig.cmsis_dsp
+    - modules/cmsis/Kconfig.cmsis_nn
   labels:
     - manifest-cmsis
 

diff --git a/arch/arm/core/aarch32/cortex_a_r/cache.c b/arch/arm/core/aarch32/cortex_a_r/cache.c
@@ -14,7 +14,7 @@
 
 #include <zephyr/kernel.h>
 #include <zephyr/cache.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/barrier.h>
 
 /* Cache Type Register */

diff --git a/arch/arm/core/aarch32/cortex_a_r/tcm.c b/arch/arm/core/aarch32/cortex_a_r/tcm.c
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 #include <zephyr/kernel.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 
 void z_arm_tcm_disable_ecc(void)
 {

diff --git a/arch/arm/core/aarch32/cortex_a_r/thread.c b/arch/arm/core/aarch32/cortex_a_r/thread.c
@@ -5,7 +5,7 @@
  */
 
 #include <stdbool.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 
 bool z_arm_thread_is_in_user_mode(void)
 {

diff --git a/arch/arm/core/aarch32/cortex_m/cache.c b/arch/arm/core/aarch32/cortex_m/cache.c
@@ -13,7 +13,7 @@
 
 #include <zephyr/arch/cpu.h>
 #include <zephyr/cache.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 void arch_dcache_enable(void)
 {

diff --git a/arch/arm/core/aarch32/cortex_m/fpu.c b/arch/arm/core/aarch32/cortex_m/fpu.c
@@ -6,7 +6,7 @@
  */
 
 #include <zephyr/kernel.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/arch/arm/aarch32/cortex_m/fpu.h>
 
 /**

diff --git a/arch/arm/core/aarch32/cortex_m/irq_init.c b/arch/arm/core/aarch32/cortex_m/irq_init.c
@@ -11,7 +11,7 @@
  */
 
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 /**
  *

diff --git a/arch/arm/core/aarch32/cortex_m/scb.c b/arch/arm/core/aarch32/cortex_m/scb.c
@@ -18,7 +18,7 @@
 #include <zephyr/arch/cpu.h>
 #include <zephyr/sys/util.h>
 #include <zephyr/sys/barrier.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/linker/linker-defs.h>
 #include <zephyr/cache.h>
 

diff --git a/arch/arm/core/aarch32/cortex_m/thread.c b/arch/arm/core/aarch32/cortex_m/thread.c
@@ -5,7 +5,7 @@
  */
 
 #include <stdbool.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 bool z_arm_thread_is_in_user_mode(void)
 {

diff --git a/arch/arm/core/aarch32/cortex_m/timing.c b/arch/arm/core/aarch32/cortex_m/timing.c
@@ -15,7 +15,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/timing/timing.h>
 #include <aarch32/cortex_m/dwt.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys_clock.h>
 
 /**

diff --git a/arch/arm/core/aarch32/cortex_m/tz/arm_core_tz.c b/arch/arm/core/aarch32/cortex_m/tz/arm_core_tz.c
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <aarch32/cortex_m/tz.h>
 #include <aarch32/cortex_m/exc.h>
 

diff --git a/arch/arm/core/aarch32/irq_manage.c b/arch/arm/core/aarch32/irq_manage.c
@@ -17,7 +17,7 @@
 #include <zephyr/kernel.h>
 #include <zephyr/arch/cpu.h>
 #if defined(CONFIG_CPU_CORTEX_M)
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #elif defined(CONFIG_CPU_AARCH32_CORTEX_A) \
 	|| defined(CONFIG_CPU_AARCH32_CORTEX_R)
 #include <zephyr/drivers/interrupt_controller/gic.h>

diff --git a/arch/arm/core/aarch32/mmu/arm_mmu.c b/arch/arm/core/aarch32/mmu/arm_mmu.c
@@ -29,7 +29,7 @@
 #include <zephyr/sys/mem_manage.h>
 #include <zephyr/sys/barrier.h>
 
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
+#include <cmsis_core.h>
 
 #include <zephyr/arch/arm/aarch32/mmu/arm_mmu.h>
 #include "arm_mmu_priv.h"

diff --git a/arch/arm/include/aarch32/cortex_m/dwt.h b/arch/arm/include/aarch32/cortex_m/dwt.h
@@ -20,7 +20,7 @@
 
 #else
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/sys/__assert.h>
 
 #ifdef __cplusplus

diff --git a/arch/arm/include/aarch32/cortex_m/exc.h b/arch/arm/include/aarch32/cortex_m/exc.h
@@ -22,7 +22,7 @@
 
 #else
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/arch/arm/aarch32/exc.h>
 #include <zephyr/irq_offload.h>
 

diff --git a/arch/arm/include/aarch32/cortex_m/stack.h b/arch/arm/include/aarch32/cortex_m/stack.h
@@ -20,7 +20,7 @@
 
 #else
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #ifdef __cplusplus
 extern "C" {

diff --git a/boards/arm/arty/board.c b/boards/arm/arty/board.c
@@ -4,7 +4,7 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/device.h>
 #include <zephyr/devicetree.h>
 #include <zephyr/drivers/gpio.h>

diff --git a/drivers/cache/cache_aspeed.c b/drivers/cache/cache_aspeed.c
@@ -5,7 +5,6 @@
  */
 
 #include <zephyr/kernel.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/drivers/syscon.h>
 #include <zephyr/sys/barrier.h>
 

diff --git a/drivers/clock_control/clock_control_mchp_xec.c b/drivers/clock_control/clock_control_mchp_xec.c
@@ -8,7 +8,7 @@
 
 #include <soc.h>
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/drivers/clock_control/mchp_xec_clock_control.h>
 #include <zephyr/drivers/pinctrl.h>

diff --git a/drivers/display/display_stm32_ltdc.c b/drivers/display/display_stm32_ltdc.c
@@ -55,7 +55,7 @@ LOG_MODULE_REGISTER(display_stm32_ltdc, CONFIG_DISPLAY_LOG_LEVEL);
 #endif
 
 #if defined(CONFIG_HAS_CMSIS_CORE_M)
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #if __DCACHE_PRESENT == 1
 #define CACHE_INVALIDATE(addr, size)	SCB_InvalidateDCache_by_Addr((addr), (size))

diff --git a/drivers/gpio/gpio_mchp_xec_v2.c b/drivers/gpio/gpio_mchp_xec_v2.c
@@ -13,7 +13,6 @@
 #include <zephyr/dt-bindings/gpio/gpio.h>
 #include <zephyr/dt-bindings/pinctrl/mchp-xec-pinctrl.h>
 #include <soc.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
 #include <zephyr/irq.h>
 
 #include <zephyr/drivers/gpio/gpio_utils.h>

diff --git a/drivers/interrupt_controller/intc_mchp_ecia_xec.c b/drivers/interrupt_controller/intc_mchp_ecia_xec.c
@@ -13,7 +13,7 @@
 #define DT_DRV_COMPAT microchip_xec_ecia
 
 #include <zephyr/arch/cpu.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/device.h>
 #include <soc.h>
 #include <zephyr/sys/__assert.h>

diff --git a/drivers/kscan/kscan_mchp_xec.c b/drivers/kscan/kscan_mchp_xec.c
@@ -6,7 +6,7 @@
 
 #define DT_DRV_COMPAT microchip_xec_kscan
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <errno.h>
 #include <zephyr/device.h>
 #ifdef CONFIG_SOC_SERIES_MEC172X

diff --git a/drivers/ps2/ps2_mchp_xec.c b/drivers/ps2/ps2_mchp_xec.c
@@ -7,7 +7,7 @@
 
 #define DT_DRV_COMPAT microchip_xec_ps2
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <errno.h>
 #include <zephyr/device.h>
 #include <zephyr/kernel.h>

diff --git a/drivers/serial/uart_lpc11u6x.c b/drivers/serial/uart_lpc11u6x.c
@@ -5,7 +5,7 @@
  */
 #define DT_DRV_COMPAT nxp_lpc11u6x_uart
 
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 
 #include <zephyr/drivers/uart.h>
 #include <zephyr/drivers/clock_control.h>

diff --git a/drivers/timer/cortex_m_systick.c b/drivers/timer/cortex_m_systick.c
@@ -7,7 +7,7 @@
 #include <zephyr/drivers/timer/system_timer.h>
 #include <zephyr/sys_clock.h>
 #include <zephyr/spinlock.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/irq.h>
 #include <zephyr/sys/util.h>
 

diff --git a/drivers/timer/mchp_xec_rtos_timer.c b/drivers/timer/mchp_xec_rtos_timer.c
@@ -12,7 +12,7 @@
 #include <zephyr/drivers/timer/system_timer.h>
 #include <zephyr/sys_clock.h>
 #include <zephyr/spinlock.h>
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+#include <cmsis_core.h>
 #include <zephyr/irq.h>
 
 BUILD_ASSERT(!IS_ENABLED(CONFIG_SMP), "XEC RTOS timer doesn't support SMP");

diff --git a/include/zephyr/arch/arm/aarch32/barrier.h b/include/zephyr/arch/arm/aarch32/barrier.h
@@ -10,11 +10,7 @@
 #error Please include <zephyr/sys/barrier.h>
 #endif
 
-#if defined(CONFIG_CPU_CORTEX_M)
-#include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
-#else
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
-#endif
+#include <cmsis_core.h>
 
 #ifdef __cplusplus
 extern "C" {

diff --git a/include/zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h b/include/zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h
@@ -1,66 +1,13 @@
 /*
- * Copyright (c) 2020 Stephanos Ioannidis <[email protected]>
- *
+ * Copyright (c) 2023 Nordic Semiconductor ASA
  * SPDX-License-Identifier: Apache-2.0
  */
 
-/**
- * @file
- * @brief CMSIS interface file
- *
- * This header contains the interface to the ARM CMSIS Core headers.
- */
-
-#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_
-#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_
-
-#include <soc.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#ifndef __CR_REV
-#define __CR_REV                0U
-#endif
-
-#ifndef __CA_REV
-#define __CA_REV                0U
-#endif
+#ifndef ZEPHYR_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_
+#define ZEPHYR_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_
 
-#ifndef __FPU_PRESENT
-#define __FPU_PRESENT           CONFIG_CPU_HAS_FPU
-#endif
-
-#ifndef __MMU_PRESENT
-#define __MMU_PRESENT           CONFIG_CPU_HAS_MMU
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#if defined(CONFIG_CPU_CORTEX_R4)
-#include <core_cr4.h>
-#elif defined(CONFIG_CPU_CORTEX_R5)
-#include <core_cr5.h>
-#elif defined(CONFIG_CPU_CORTEX_R7)
-#include <core_cr7.h>
-#elif defined(CONFIG_CPU_CORTEX_R52)
-#include <core_cr52.h>
-#elif defined(CONFIG_CPU_AARCH32_CORTEX_A)
-/*
- * Any defines relevant for the proper inclusion of CMSIS' Cortex-A
- * Common Peripheral Access Layer (such as __CORTEX_A) which are not
- * covered by the Kconfig-based default assignments above must be
- * provided by each aarch32 Cortex-A SoC's header file (already in-
- * cluded above).
- */
-#include <core_ca.h>
-#else
-#error "Unknown device"
-#endif
+#include <cmsis_core.h>
 
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis_ext.h>
+#warning This header is deprecated, please include <cmsis_core.h>
 
-#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_ */
+#endif /* ZEPHYR_ARCH_ARM_AARCH32_CORTEX_A_R_CMSIS_H_ */
diff --git a/include/zephyr/arch/arm/aarch32/cortex_a_r/sys_io.h b/include/zephyr/arch/arm/aarch32/cortex_a_r/sys_io.h
@@ -16,7 +16,6 @@
 
 #include <zephyr/types.h>
 #include <zephyr/sys/sys_io.h>
-#include <zephyr/arch/arm/aarch32/cortex_a_r/cmsis.h>
 #include <zephyr/sys/barrier.h>
 
 #ifdef __cplusplus
-Original file line number
+Diff line change
@@ Expand Up / @@ -11,7 +11,7 @@ @@
      */
     #include <zephyr/arch/cpu.h>
-    #include <zephyr/arch/arm/aarch32/cortex_m/cmsis.h>
+    #include <cmsis_core.h>
     /**
      *
@@ Expand Down @@