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Initial support for EFR32BG22 #50352
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Initial support for EFR32BG22 #50352
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@sateeshkotapati ping FYI |
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The following west manifest projects have been modified in this Pull Request:
Note: This message is automatically posted and updated by the Manifest GitHub Action. |
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gmarull
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A few comments. PM code needs, at least, a better explanation.
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@gmarull thank you for your review. I've already addressed most of the comments. After positive review I will squash fixes with initial set of commits from this PR. |
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This bumps the hal_silabs in order to add initial support for EFR32BG22 SoCs Signed-off-by: Paweł Czarnecki <[email protected]>
It would be better to use GPIO_PinModeSet() functions directly in the drivers. Signed-off-by: Pawel Czarnecki <[email protected]>
This commit adds initial support for gecko pinctrl driver Co-authored-by: Mateusz Sierszulski <[email protected]> Signed-off-by: Filip Kokosinski <[email protected]>
This commit adds a series of driver-related changes to Gecko pinctrl. Co-authored-by: Mateusz Sierszulski <[email protected]> Signed-off-by: Filip Kokosinski <[email protected]>
This commit adds initial support for Silabs Real-Time counter Co-authored-by: Filip Kokosinski <[email protected]> Signed-off-by: Mateusz Sierszulski <[email protected]>
This commit adds sample support for the counter_gecko_stimer driver. Signed-off-by: Mateusz Sierszulski <[email protected]>
…timer This commit adds test support for the counter_gecko_stimer driver. Signed-off-by: Mateusz Sierszulski <[email protected]>
Common GPIO driver needs to be initialized before e.g UART driver to ensure correct GPIO clock configuration when configuring UART pinout Signed-off-by: Pawel Czarnecki <[email protected]>
Enable GPIO clock so that other drivers could configure their I/O pins Signed-off-by: Pawel Czarnecki <[email protected]>
This commit adds support for Silicon Labs EFR32BG22 SoC. Co-authored-by: Mateusz Sierszulski <[email protected]> Signed-off-by: Filip Kokosinski <[email protected]>
This commit adds support for Silicon Labs efr32bg22_sltb010a boardo Co-authored-by: Mateusz Sierszulski <[email protected]> Co-authored-by: Pawel Czarnecki <[email protected]> Signed-off-by: Filip Kokosinski <[email protected]> Signed-off-by: Paweł Czarnecki <[email protected]>
HAL update affects also EFR32MG21 SoC. Because of that we need to update the reg addresses in DTS. Signed-off-by: Pawel Czarnecki <[email protected]>
change GPIO_IntConfig to GPIO_ExtIntConfig Signed-off-by: Paweł Czarnecki <[email protected]>
do not build hwinfo driver for this board - it does not have support for it Signed-off-by: Mateusz Sierszulski <[email protected]>
Add missing include Signed-off-by: Pawel Czarnecki <[email protected]>
peripheral-id property should be eventually removed entirely. For now set it as optional and allow skipping the usage in GPIO driver. Signed-off-by: Pawel Czarnecki <[email protected]>
peripheral-id property should be eventually removed. For now set it as optional and allow skipping the usage in UART driver. Signed-off-by: Pawel Czarnecki <[email protected]>
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Hi @gmarull, @cfriedt, @alexanderwachter. HAL PR has been merged. I rebased the PR and updated HAL sha in |
cfriedt
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Just pointed out some required: false instances in Device Tree YAML, but not blocking. If you need to go through another rev then fix, otherwise, fix later.
| peripheral-id: | ||
| type: int | ||
| required: true | ||
| required: false |
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This is redundant - should have been caught by CI ..
| peripheral-id: | ||
| type: int | ||
| required: true | ||
| required: false |
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This is redundant as well.
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@lpawelcz This seems to have broken multiple networking tests: https://github.com/zephyrproject-rtos/zephyr/pull/52852/checks?check_run_id=10231260430. Can you provide a fix? |
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@stephanosio I'll take a look if nobody else is working on it atm |
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@stephanosio @cfriedt I have the fix already. Give me a second and I will open a PR |
This PR supersedes PR #35361 and is a minimal version thereof. Its main purpose is to introduce basic support for the BRD4184B board using the EFR32BG22 SoC.
The PR consists of:
Initial support was verified on hardware by running the following samples:
This PR should be merged only after zephyrproject-rtos/hal_silabs#19 is merged and
hal_silabsrevision in west.yml is bumped to the newest one.