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drivers: counter: Add SAM0 basic counter support #15105
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Nice work!
Thinking about it there is nothing that requires both timers to occupy consecutive bits in MCLK. With this, |
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Note that the Kconfig error is due to token pasting ( |
benpicco
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tested both on samr21-xpro and same54-xpro
This makes use of the counter driver from zephyrproject-rtos#15105 tc_fixup_samd5x.h was generated by for i in {0..6..2}; do for n in {A..D}; do echo "#ifdef MCLK_APB${n}MASK_TC${i}" echo "#define MCLK_TC${i} (&MCLK->APB${n}MASK.reg)" echo "#define MCLK_TC${i}_MASK " \ "((1 << MCLK_APB${n}MASK_TC${i}_Pos)" \ "| (1 << MCLK_APB${n}MASK_TC$(($i+1))_Pos))" echo "#endif" done echo "" done Signed-off-by: Benjamin Valentin <[email protected]>
This makes use of the counter driver from zephyrproject-rtos#15105 tc_fixup_samd5x.h was generated by for i in {0..6..2}; do for n in {A..D}; do echo "#ifdef MCLK_APB${n}MASK_TC${i}" echo "#define MCLK_TC${i} (&MCLK->APB${n}MASK.reg)" echo "#define MCLK_TC${i}_MASK " \ "((1 << MCLK_APB${n}MASK_TC${i}_Pos)" \ "| (1 << MCLK_APB${n}MASK_TC$(($i+1))_Pos))" echo "#endif" done echo "" done Signed-off-by: Benjamin Valentin <[email protected]>
This adds support for the basic timer counter (TC) found on SAM0 series parts. This driver only supports running the counter in 32 bit wide mode. Since this mode explicitly slaves the odd counters to the even ones, only instances of the even ones are defined. Tested with tests/drivers/counter/counter_basic_api on SAMD21. Signed-off-by: Derek Hageman <[email protected]>
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I think the prescaler selection should go into the device tree - but I suppose you will touch up on this anyway once #15585 is merged. |
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Yeah, I'd do a However, once the SoC clock tree is not an immutable thing, the prescaler should be configured the same way: meaning device tree specification and calculation derived from the requested frequency. |
nordic-krch
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looks ok
This makes use of the counter driver from zephyrproject-rtos#15105 tc_fixup_samd5x.h was generated by for i in {0..6..2}; do for n in {A..D}; do echo "#ifdef MCLK_APB${n}MASK_TC${i}" echo "#define MCLK_TC${i} (&MCLK->APB${n}MASK.reg)" echo "#define MCLK_TC${i}_MASK " \ "((1 << MCLK_APB${n}MASK_TC${i}_Pos)" \ "| (1 << MCLK_APB${n}MASK_TC$(($i+1))_Pos))" echo "#endif" done echo "" done Signed-off-by: Benjamin Valentin <[email protected]>
This adds support for the basic timer counter (TC) found on SAM0 series parts. This driver only supports running the counter in 32 bit wide mode. Since this mode explicitly slaves the odd counters to the even ones, only instances of the even ones are defined.
Tested with
tests/drivers/counter/counter_basic_apion SAMD21.Compile tested on SAMR21 and SAMD20.
but requires #15104 (and a bit of rebasing if that's merged)This will also require a trivial rebase if #14794 is merged (the parameter is already there, just currently set to a default).
@benpicco: I compile tested this against SAME54, but you'd need to generate a
tc_fixup_samd5x.hin the spirit of the sercom one. I just used the static definition: