SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)

Verilog VPI module to dump FST (Fast Signal Trace) databases

A RISC-V based CPU in SystemVerilog

This is a list of central processing units based on the ARM family of instruction sets designed by ARM Ltd. and third parties, sorted by version of the ARM instruction set, release and name. In 2005, ARM provided a summary of the numerous vendors who implement ARM cores in their design.

Open-source RHBD (Radiation Hardened by Design) Standard-Cell Library for SKY130

OoO 6-stage CPU (rv32imac_zicntr_zicsr_zifencei).

RTL implementation of RISC-V RV32EMC

Simple microprocessor in SystemVerilog.

Using Nim to interface with Verilog and SystemVerilog test benches via VPI

System for Cyclone IV FPGA dev board that consist of RISC-V CPU, custom OS, DMA, controllers and drivers for peripherals.

FPGA implemented component for realize register file in FPGA resources with request and sends data to ADXL345 device

The traffic speed control system for the MetroTechno systems set.

SHA-1 implementation on Nios II soft-core processor with C and SystemVerilog.

The speeding violations control system for the MetroTechno systems set.

Yet another RISC-V CPU core

HF-RISC SoC

Hardware Description Languages

Multiplayer tank game implemented on the DE1-SoC Cyclone V FPGA. Based on Battle City for the NES, runs with 2 controllers, uses VGA for video and the WM8731 CODEC for audio.

Minimal SoC design for alarm clock

Learning Verilog/SystemVerilog