This repo serves as a tracker for my Verilog/SystemVerilog progress.

Some of the earlier projects, labeled as Labs (Lab02 not included) are projects that were originally written in VHDL. However, they have been redefined in Verilog/SystemVerilog with techniques that I learned in digital design. You may encounter heavy use of comments in some of the earlier labs as they are for my own reference. They also serve to help others understand some of the benefits that Verilog/SystemVerilog have over VHDL.

In each project, I aim to utilize as many new features of Verilog/SystemVerilog to help make learning more effective. This is my take on learning Verilog/SystemVerilog and it may not be effective for more experienced programmers.

If you have learned something from this, that's awesome! 😄😄😄 Thanks for viewing!