Fix level-zero vector width queries #2722
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Previous implementation was returning native and preferred vector widths using an heuristic based on native simd width. On simd8 GPUs (Intel Arc Alchemist and Flex Series), this approach is incorrect and doesn't match what OpenCL returns. This set of changes aligns the behavior with OpenCL, defined here: https://github.com/intel/compute-runtime/blob/291745cdf76d83f5dc40e7ef41d347366235ccdb/opencl/source/cl_device/cl_device_caps.cpp#L236
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Hello @ph0b , you will want to move this to: Unified Runtime -> intel/llvm Repo Move Notice The code will be mirrored to oneapi-src/unified-runtime and the specification will continue to be hosted at oneapi-src.github.io/unified-runtime. The contribution guide has been updated with new instructions for contributing to Unified Runtime. PR Migration Should you wish to continue with your PR you will need to migrate it to intel/llvm. |
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Hello @nrspruit, |
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Previous implementation was returning native and preferred vector widths using an heuristic based on native simd width.
Especially on simd8 GPUs (Intel Arc Alchemist and Flex Series), this approach is incorrect and doesn't match what OpenCL returns.
This set of changes aligns the behavior with OpenCL, defined here: https://github.com/intel/compute-runtime/blob/291745cdf76d83f5dc40e7ef41d347366235ccdb/opencl/source/cl_device/cl_device_caps.cpp#L236