[UR][L0] Fix level-zero vector width queries #17178
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nrspruit
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Feb 25, 2025
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nrspruit
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LGTM until we have a better method to unify the values reported.
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Hello @nrspruit, are you planning to get this merged? It's been over a month since you've approved. If you expected me to do something, please be aware I don't have write access. |
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Once a patch has been approved, the author needs to ask gatekeepers (@ intel/llvm-gatekeepers) for a merge. |
Returning native and preferred vector widths using an heuristic based on native simd width is incorrect. Especially on simd8 GPUs (Intel Arc Alchemist and Flex Series), this approach doesn't match what OpenCL returns. This set of changes aligns the behavior with OpenCL, defined here: https://github.com/intel/compute-runtime/blob/291745cdf76d83f5dc40e7ef41d347366235ccdb/opencl/source/cl_device/cl_device_caps.cpp#L236
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Thanks @pbalcer for the clarification. @intel/llvm-gatekeepers can you get this PR merged? |
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Returning native and preferred vector widths using an heuristic based on native simd width is incorrect.
Especially on simd8 GPUs (Intel Arc Alchemist and Flex Series), this approach doesn't match what OpenCL returns.
This set of changes aligns the behavior with OpenCL, defined here: https://github.com/intel/compute-runtime/blob/291745cdf76d83f5dc40e7ef41d347366235ccdb/opencl/source/cl_device/cl_device_caps.cpp#L236