[mlir][spirv][doc] Remove duplicate syntax formats #73386
Merged
Conversation
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
|
@llvm/pr-subscribers-mlir-spirv @llvm/pr-subscribers-mlir Author: Rik Huijzer (rikhuijzer) ChangesSome operations defined their syntax both in the documentation and via The strategy that I used to find the duplicates was pretty uncomplicated. I scrolled through the SPIR-V Dialect page and removed all syntax which was below a This strategy works because the llvm-project/mlir/tools/mlir-tblgen/OpDocGen.cpp Lines 108 to 124 in e970652 llvm-project/mlir/tools/mlir-tblgen/OpDocGen.cpp Lines 197 to 199 in e970652 Patch is 109.55 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/73386.diff 18 Files Affected:
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td
index c4d1e01f9feef83..c55a991350482b1 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVArithmeticOps.td
@@ -88,18 +88,11 @@ def SPIRV_FAddOp : SPIRV_ArithmeticBinaryOp<"FAdd", SPIRV_Float, [Commutative]>
let description = [{
Result Type must be a scalar or vector of floating-point type.
- The types of Operand 1 and Operand 2 both must be the same as Result
+ The types of Operand 1 and Operand 2 both must be the same as Result
Type.
- Results are computed per component.
+ Results are computed per component.
- <!-- End of AutoGen section -->
- ```
- float-scalar-vector-type ::= float-type |
- `vector<` integer-literal `x` float-type `>`
- fadd-op ::= ssa-id `=` `spirv.FAdd` ssa-use, ssa-use
- `:` float-scalar-vector-type
- ```
#### Example:
```mlir
@@ -117,20 +110,12 @@ def SPIRV_FDivOp : SPIRV_ArithmeticBinaryOp<"FDiv", SPIRV_Float, []> {
let description = [{
Result Type must be a scalar or vector of floating-point type.
- The types of Operand 1 and Operand 2 both must be the same as Result
+ The types of Operand 1 and Operand 2 both must be the same as Result
Type.
- Results are computed per component. The resulting value is undefined
+ Results are computed per component. The resulting value is undefined
if Operand 2 is 0.
- <!-- End of AutoGen section -->
- ```
- float-scalar-vector-type ::= float-type |
- `vector<` integer-literal `x` float-type `>`
- fdiv-op ::= ssa-id `=` `spirv.FDiv` ssa-use, ssa-use
- `:` float-scalar-vector-type
- ```
-
#### Example:
```mlir
@@ -150,21 +135,14 @@ def SPIRV_FModOp : SPIRV_ArithmeticBinaryOp<"FMod", SPIRV_Float, []> {
let description = [{
Result Type must be a scalar or vector of floating-point type.
- The types of Operand 1 and Operand 2 both must be the same as Result
+ The types of Operand 1 and Operand 2 both must be the same as Result
Type.
- Results are computed per component. The resulting value is undefined
+ Results are computed per component. The resulting value is undefined
if Operand 2 is 0. Otherwise, the result is the remainder r of Operand
1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the
sign of Operand 2.
- <!-- End of AutoGen section -->
- ```
- float-scalar-vector-type ::= float-type |
- `vector<` integer-literal `x` float-type `>`
- fmod-op ::= ssa-id `=` `spirv.FMod` ssa-use, ssa-use
- `:` float-scalar-vector-type
- ```
#### Example:
```mlir
@@ -182,19 +160,10 @@ def SPIRV_FMulOp : SPIRV_ArithmeticBinaryOp<"FMul", SPIRV_Float, [Commutative]>
let description = [{
Result Type must be a scalar or vector of floating-point type.
- The types of Operand 1 and Operand 2 both must be the same as Result
+ The types of Operand 1 and Operand 2 both must be the same as Result
Type.
- Results are computed per component.
-
- <!-- End of AutoGen section -->
-
- ```
- float-scalar-vector-type ::= float-type |
- `vector<` integer-literal `x` float-type `>`
- fmul-op ::= `spirv.FMul` ssa-use, ssa-use
- `:` float-scalar-vector-type
- ```
+ Results are computed per component.
#### Example:
@@ -218,17 +187,9 @@ def SPIRV_FNegateOp : SPIRV_ArithmeticUnaryOp<"FNegate", SPIRV_Float, []> {
let description = [{
Result Type must be a scalar or vector of floating-point type.
- The type of Operand must be the same as Result Type.
-
- Results are computed per component.
-
- <!-- End of AutoGen section -->
+ The type of Operand must be the same as Result Type.
- ```
- float-scalar-vector-type ::= float-type |
- `vector<` integer-literal `x` float-type `>`
- fmul-op ::= `spirv.FNegate` ssa-use `:` float-scalar-vector-type
- ```
+ Results are computed per component.
#### Example:
@@ -249,22 +210,14 @@ def SPIRV_FRemOp : SPIRV_ArithmeticBinaryOp<"FRem", SPIRV_Float, []> {
let description = [{
Result Type must be a scalar or vector of floating-point type.
- The types of Operand 1 and Operand 2 both must be the same as Result
+ The types of Operand 1 and Operand 2 both must be the same as Result
Type.
- Results are computed per component. The resulting value is undefined
+ Results are computed per component. The resulting value is undefined
if Operand 2 is 0. Otherwise, the result is the remainder r of Operand
1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the
sign of Operand 1.
- <!-- End of AutoGen section -->
- ```
- float-scalar-vector-type ::= float-type |
- `vector<` integer-literal `x` float-type `>`
- frem-op ::= ssa-id `=` `spirv.FRemOp` ssa-use, ssa-use
- `:` float-scalar-vector-type
- ```
-
#### Example:
```mlir
@@ -282,18 +235,10 @@ def SPIRV_FSubOp : SPIRV_ArithmeticBinaryOp<"FSub", SPIRV_Float, []> {
let description = [{
Result Type must be a scalar or vector of floating-point type.
- The types of Operand 1 and Operand 2 both must be the same as Result
+ The types of Operand 1 and Operand 2 both must be the same as Result
Type.
- Results are computed per component.
-
- <!-- End of AutoGen section -->
- ```
- float-scalar-vector-type ::= float-type |
- `vector<` integer-literal `x` float-type `>`
- fsub-op ::= ssa-id `=` `spirv.FRemOp` ssa-use, ssa-use
- `:` float-scalar-vector-type
- ```
+ Results are computed per component.
#### Example:
@@ -314,7 +259,7 @@ def SPIRV_IAddOp : SPIRV_ArithmeticBinaryOp<"IAdd",
let description = [{
Result Type must be a scalar or vector of integer type.
- The type of Operand 1 and Operand 2 must be a scalar or vector of
+ The type of Operand 1 and Operand 2 must be a scalar or vector of
integer type. They must have the same number of components as Result
Type. They must have the same component width as Result Type.
@@ -322,15 +267,7 @@ def SPIRV_IAddOp : SPIRV_ArithmeticBinaryOp<"IAdd",
result R, where N is the component width and R is computed with enough
precision to avoid overflow and underflow.
- Results are computed per component.
-
- <!-- End of AutoGen section -->
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- iadd-op ::= ssa-id `=` `spirv.IAdd` ssa-use, ssa-use
- `:` integer-scalar-vector-type
- ```
+ Results are computed per component.
#### Example:
@@ -391,7 +328,7 @@ def SPIRV_IMulOp : SPIRV_ArithmeticBinaryOp<"IMul",
let description = [{
Result Type must be a scalar or vector of integer type.
- The type of Operand 1 and Operand 2 must be a scalar or vector of
+ The type of Operand 1 and Operand 2 must be a scalar or vector of
integer type. They must have the same number of components as Result
Type. They must have the same component width as Result Type.
@@ -399,15 +336,7 @@ def SPIRV_IMulOp : SPIRV_ArithmeticBinaryOp<"IMul",
result R, where N is the component width and R is computed with enough
precision to avoid overflow and underflow.
- Results are computed per component.
-
- <!-- End of AutoGen section -->
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- imul-op ::= ssa-id `=` `spirv.IMul` ssa-use, ssa-use
- `:` integer-scalar-vector-type
- ```
+ Results are computed per component.
#### Example:
@@ -431,7 +360,7 @@ def SPIRV_ISubOp : SPIRV_ArithmeticBinaryOp<"ISub",
let description = [{
Result Type must be a scalar or vector of integer type.
- The type of Operand 1 and Operand 2 must be a scalar or vector of
+ The type of Operand 1 and Operand 2 must be a scalar or vector of
integer type. They must have the same number of components as Result
Type. They must have the same component width as Result Type.
@@ -439,15 +368,7 @@ def SPIRV_ISubOp : SPIRV_ArithmeticBinaryOp<"ISub",
result R, where N is the component width and R is computed with enough
precision to avoid overflow and underflow.
- Results are computed per component.
-
- <!-- End of AutoGen section -->
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- isub-op ::= `spirv.ISub` ssa-use, ssa-use
- `:` integer-scalar-vector-type
- ```
+ Results are computed per component.
#### Example:
@@ -511,21 +432,13 @@ def SPIRV_SDivOp : SPIRV_ArithmeticBinaryOp<"SDiv",
let description = [{
Result Type must be a scalar or vector of integer type.
- The type of Operand 1 and Operand 2 must be a scalar or vector of
+ The type of Operand 1 and Operand 2 must be a scalar or vector of
integer type. They must have the same number of components as Result
Type. They must have the same component width as Result Type.
- Results are computed per component. The resulting value is undefined
+ Results are computed per component. The resulting value is undefined
if Operand 2 is 0.
- <!-- End of AutoGen section -->
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- sdiv-op ::= ssa-id `=` `spirv.SDiv` ssa-use, ssa-use
- `:` integer-scalar-vector-type
- ```
-
#### Example:
```mlir
@@ -549,22 +462,15 @@ def SPIRV_SModOp : SPIRV_ArithmeticBinaryOp<"SMod",
let description = [{
Result Type must be a scalar or vector of integer type.
- The type of Operand 1 and Operand 2 must be a scalar or vector of
+ The type of Operand 1 and Operand 2 must be a scalar or vector of
integer type. They must have the same number of components as Result
Type. They must have the same component width as Result Type.
- Results are computed per component. The resulting value is undefined
+ Results are computed per component. The resulting value is undefined
if Operand 2 is 0. Otherwise, the result is the remainder r of Operand
1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the
sign of Operand 2.
- <!-- End of AutoGen section -->
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- smod-op ::= ssa-id `=` `spirv.SMod` ssa-use, ssa-use
- `:` integer-scalar-vector-type
- ```
#### Example:
```mlir
@@ -649,22 +555,15 @@ def SPIRV_SRemOp : SPIRV_ArithmeticBinaryOp<"SRem",
let description = [{
Result Type must be a scalar or vector of integer type.
- The type of Operand 1 and Operand 2 must be a scalar or vector of
+ The type of Operand 1 and Operand 2 must be a scalar or vector of
integer type. They must have the same number of components as Result
Type. They must have the same component width as Result Type.
- Results are computed per component. The resulting value is undefined
+ Results are computed per component. The resulting value is undefined
if Operand 2 is 0. Otherwise, the result is the remainder r of Operand
1 divided by Operand 2 where if r ≠ 0, the sign of r is the same as the
sign of Operand 1.
- <!-- End of AutoGen section -->
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- srem-op ::= ssa-id `=` `spirv.SRem` ssa-use, ssa-use
- `:` integer-scalar-vector-type
- ```
#### Example:
```mlir
@@ -686,25 +585,17 @@ def SPIRV_UDivOp : SPIRV_ArithmeticBinaryOp<"UDiv",
Result Type must be a scalar or vector of integer type, whose Signedness
operand is 0.
- The types of Operand 1 and Operand 2 both must be the same as Result
+ The types of Operand 1 and Operand 2 both must be the same as Result
Type.
- Results are computed per component. The resulting value is undefined
+ Results are computed per component. The resulting value is undefined
if Operand 2 is 0.
- <!-- End of AutoGen section -->
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- udiv-op ::= ssa-id `=` `spirv.UDiv` ssa-use, ssa-use
- `:` integer-scalar-vector-type
- ```
#### Example:
```mlir
%4 = spirv.UDiv %0, %1 : i32
%5 = spirv.UDiv %2, %3 : vector<4xi32>
-
```
}];
}
@@ -789,25 +680,17 @@ def SPIRV_UModOp : SPIRV_ArithmeticBinaryOp<"UMod",
Result Type must be a scalar or vector of integer type, whose Signedness
operand is 0.
- The types of Operand 1 and Operand 2 both must be the same as Result
+ The types of Operand 1 and Operand 2 both must be the same as Result
Type.
- Results are computed per component. The resulting value is undefined
+ Results are computed per component. The resulting value is undefined
if Operand 2 is 0.
- <!-- End of AutoGen section -->
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- umod-op ::= ssa-id `=` `spirv.UMod` ssa-use, ssa-use
- `:` integer-scalar-vector-type
- ```
#### Example:
```mlir
%4 = spirv.UMod %0, %1 : i32
%5 = spirv.UMod %2, %3 : vector<4xi32>
-
```
}];
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBarrierOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBarrierOps.td
index afdae093e6316a6..1ebea94fced0a35 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBarrierOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBarrierOps.td
@@ -51,21 +51,10 @@ def SPIRV_ControlBarrierOp : SPIRV_Op<"ControlBarrier", []> {
OpControlBarrier will be visible to any other invocation after return
from that OpControlBarrier.
- <!-- End of AutoGen section -->
-
- ```
- scope ::= `"CrossDevice"` | `"Device"` | `"Workgroup"` | ...
-
- memory-semantics ::= `"None"` | `"Acquire"` | "Release"` | ...
-
- control-barrier-op ::= `spirv.ControlBarrier` scope, scope, memory-semantics
- ```
-
#### Example:
```mlir
spirv.ControlBarrier "Workgroup", "Device", "Acquire|UniformMemory"
-
```
}];
@@ -102,21 +91,10 @@ def SPIRV_MemoryBarrierOp : SPIRV_Op<"MemoryBarrier", []> {
To execute both a memory barrier and a control barrier, see
OpControlBarrier.
- <!-- End of AutoGen section -->
-
- ```
- scope ::= `"CrossDevice"` | `"Device"` | `"Workgroup"` | ...
-
- memory-semantics ::= `"None"` | `"Acquire"` | `"Release"` | ...
-
- memory-barrier-op ::= `spirv.MemoryBarrier` scope, memory-semantics
- ```
-
#### Example:
```mlir
spirv.MemoryBarrier "Device", "Acquire|UniformMemory"
-
```
}];
diff --git a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
index 286f4de6f90f621..91b69576cd1d317 100644
--- a/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
+++ b/mlir/include/mlir/Dialect/SPIRV/IR/SPIRVBitOps.td
@@ -80,15 +80,6 @@ def SPIRV_BitCountOp : SPIRV_BitUnaryOp<"BitCount", []> {
The result is the unsigned value that is the number of bits in Base that
are 1.
- <!-- End of AutoGen section -->
-
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- bitcount-op ::= ssa-id `=` `spirv.BitCount` ssa-use
- `:` integer-scalar-vector-type
- ```
-
#### Example:
```mlir
@@ -130,17 +121,6 @@ def SPIRV_BitFieldInsertOp : SPIRV_Op<"BitFieldInsert",
The resulting value is undefined if Count or Offset or their sum is
greater than the number of bits in the result.
- <!-- End of AutoGen section -->
-
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- bitfield-insert-op ::= ssa-id `=` `spirv.BitFieldInsert` ssa-use `,` ssa-use
- `,` ssa-use `,` ssa-use
- `:` integer-scalar-vector-type
- `,` integer-type `,` integer-type
- ```
-
#### Example:
```mlir
@@ -202,17 +182,6 @@ def SPIRV_BitFieldSExtractOp : SPIRV_BitFieldExtractOp<"BitFieldSExtract",
The resulting value is undefined if Count or Offset or their sum is
greater than the number of bits in the result.
- <!-- End of AutoGen section -->
-
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- bitfield-extract-s-op ::= ssa-id `=` `spirv.BitFieldSExtract` ssa-use
- `,` ssa-use `,` ssa-use
- `:` integer-scalar-vector-type
- `,` integer-type `,` integer-type
- ```
-
#### Example:
```mlir
@@ -239,17 +208,6 @@ def SPIRV_BitFieldUExtractOp : SPIRV_BitFieldExtractOp<"BitFieldUExtract",
that there is no sign extension. The remaining bits of the result will
all be 0.
- <!-- End of AutoGen section -->
-
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- bitfield-extract-u-op ::= ssa-id `=` `spirv.BitFieldUExtract` ssa-use
- `,` ssa-use `,` ssa-use
- `:` integer-scalar-vector-type
- `,` integer-type `,` integer-type
- ```
-
#### Example:
```mlir
@@ -280,15 +238,6 @@ def SPIRV_BitReverseOp : SPIRV_BitUnaryOp<"BitReverse", []> {
The bit-number n of the result will be taken from bit-number Width - 1 -
n of Base, where Width is the OpTypeInt operand of the Result Type.
- <!-- End of AutoGen section -->
-
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- bitreverse-op ::= ssa-id `=` `spirv.BitReverse` ssa-use
- `:` integer-scalar-vector-type
- ```
-
#### Example:
```mlir
@@ -322,15 +271,6 @@ def SPIRV_BitwiseAndOp : SPIRV_BitBinaryOp<"BitwiseAnd",
They must have the same number of components as Result Type. They must
have the same component width as Result Type.
- <!-- End of AutoGen section -->
-
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- bitwise-and-op ::= ssa-id `=` `spirv.BitwiseAnd` ssa-use, ssa-use
- `:` integer-scalar-vector-type
- ```
-
#### Example:
```mlir
@@ -359,15 +299,6 @@ def SPIRV_BitwiseOrOp : SPIRV_BitBinaryOp<"BitwiseOr",
They must have the same number of components as Result Type. They must
have the same component width as Result Type.
- <!-- End of AutoGen section -->
-
- ```
- integer-scalar-vector-type ::= integer-type |
- `vector<` integer-literal `x` integer-type `>`
- bitwise-or-op ::= ssa-id `=` `spirv.BitwiseOr` ssa-use, ssa-use
- `:` integer-scalar-vector-type
- ```
-
...
[truncated]
|
|
Thanks for the cleanup! |
antiagainst
approved these changes
Nov 26, 2023
|
Thanks all for the nice comments! |
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Some operations defined their syntax both in the documentation and via
assemblyFormat. This leads to two syntax descriptions in the documentation for SPIR-V, see for example the documentation forspirv.mlir.yield. Since theassemblyFormatis used to generate the actual parsers and printer implementations, this PR removes the manual syntax descriptions. (Similar to #73343.)The strategy that I used to find the duplicates was pretty uncomplicated. I scrolled through the SPIR-V Dialect to find all duplicates and then remove the duplicate text from the
tdfile.Note that the
Syntax:block in the docs is a good proxy for whetherassemblyFormatis defined because it will only be generated if the op has definedassemblyFormat(op.hasAssemblyFormat()):llvm-project/mlir/tools/mlir-tblgen/OpDocGen.cpp
Lines 108 to 124 in e970652
llvm-project/mlir/tools/mlir-tblgen/OpDocGen.cpp
Lines 197 to 199 in e970652
Related issue #73359.