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[AIX] recognize vsr in inline asm for AIX #68476

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Merged
merged 3 commits into from
Oct 12, 2023
Merged

[AIX] recognize vsr in inline asm for AIX #68476

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eada8d1
[AIX] recognize vsr in inline asm for AIX
Oct 7, 2023
0d44bd3
address comments
Oct 8, 2023
4fce46b
address comments
Oct 11, 2023
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7 changes: 2 additions & 5 deletions clang/lib/Basic/Targets/PPC.cpp
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Expand Up @@ -807,7 +807,7 @@ ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
// And this mapping applies to all OSes which runs on powerpc.
// And this mapping applies to all OSes which run on powerpc.
const TargetInfo::AddlRegName GCCAddlRegNames[] = {
// Table of additional register names to use in user input.
{{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35},
Expand All @@ -829,10 +829,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
};

ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const {
if (ABI == "elfv2" || ABI == "aix")
return llvm::ArrayRef(GCCAddlRegNames);
else
return TargetInfo::getGCCAddlRegNames();
return llvm::ArrayRef(GCCAddlRegNames);
}

static constexpr llvm::StringLiteral ValidCPUNames[] = {
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3 changes: 1 addition & 2 deletions clang/lib/Basic/Targets/PPC.h
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Expand Up @@ -385,7 +385,6 @@ class LLVM_LIBRARY_VISIBILITY PPC32TargetInfo : public PPCTargetInfo {
LongDoubleWidth = 64;
LongDoubleAlign = DoubleAlign = 32;
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
ABI = "aix";
break;
default:
break;
Expand Down Expand Up @@ -419,11 +418,11 @@ class LLVM_LIBRARY_VISIBILITY PPC64TargetInfo : public PPCTargetInfo {
std::string DataLayout;

if (Triple.isOSAIX()) {
// TODO: Set appropriate ABI for AIX platform.
DataLayout = "E-m:a-Fi64-i64:64-n32:64";
LongDoubleWidth = 64;
LongDoubleAlign = DoubleAlign = 32;
LongDoubleFormat = &llvm::APFloat::IEEEdouble();
ABI = "aix";
} else if ((Triple.getArch() == llvm::Triple::ppc64le)) {
DataLayout = "e-m:e-Fn32-i64:64-n32:64";
ABI = "elfv2";
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8 changes: 5 additions & 3 deletions clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
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Expand Up @@ -2,6 +2,8 @@

// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -triple powerpc-ibm-aix -target-feature +vsx \
Expand All @@ -13,12 +15,12 @@ void testVSX (void) {
unsigned int *dbell=&a;
int d;
__asm__ __volatile__ (
"lxvw4x %%vs32, 0, %2\n\t"
"stxvw4x %%vs32, 0, %1"
"lxvw4x 32, 0, %2\n\t"
"stxvw4x 32, 0, %1"
: "=m"(*(volatile unsigned int*)(dbell))
: "r" (dbell), "r" (&d)
: "vs32"
);
}

// CHECK: call void asm sideeffect "lxvw4x %vs32, 0, $2\0A\09stxvw4x %vs32, 0, $1", "=*m,r,r,~{vs32}"
// CHECK: call void asm sideeffect "lxvw4x 32, 0, $2\0A\09stxvw4x 32, 0, $1", "=*m,r,r,~{vs32}"