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[AIX] recognize vsr in inline asm for AIX #68476

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Merged
merged 3 commits into from
Oct 12, 2023
Merged

[AIX] recognize vsr in inline asm for AIX #68476

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eada8d1
[AIX] recognize vsr in inline asm for AIX
Oct 7, 2023
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address comments
Oct 8, 2023
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Oct 11, 2023
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8 changes: 4 additions & 4 deletions clang/lib/Basic/Targets/PPC.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -753,6 +753,8 @@ void PPCTargetInfo::setFeatureEnabled(llvm::StringMap<bool> &Features,
}
}

// Make sure that registers are added in the correct array index which should be
// the DWARF number for PPC registers.
const char *const PPCTargetInfo::GCCRegNames[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "r8",
"r9", "r10", "r11", "r12", "r13", "r14", "r15", "r16", "r17",
Expand Down Expand Up @@ -807,6 +809,7 @@ ArrayRef<TargetInfo::GCCRegAlias> PPCTargetInfo::getGCCRegAliases() const {
// PPC ELFABIv2 DWARF Definitoin "Table 2.26. Mappings of Common Registers".
// vs0 ~ vs31 is mapping to 32 - 63,
// vs32 ~ vs63 is mapping to 77 - 108.
// And this mapping applies to all OSes which run on powerpc.
const TargetInfo::AddlRegName GCCAddlRegNames[] = {
// Table of additional register names to use in user input.
{{"vs0"}, 32}, {{"vs1"}, 33}, {{"vs2"}, 34}, {{"vs3"}, 35},
Expand All @@ -828,10 +831,7 @@ const TargetInfo::AddlRegName GCCAddlRegNames[] = {
};

ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const {
if (ABI == "elfv2")
return llvm::ArrayRef(GCCAddlRegNames);
else
return TargetInfo::getGCCAddlRegNames();
return llvm::ArrayRef(GCCAddlRegNames);
}

static constexpr llvm::StringLiteral ValidCPUNames[] = {
Expand Down
12 changes: 9 additions & 3 deletions clang/test/CodeGen/PowerPC/inline-asm-matching-ppc-vsx.c
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Expand Up @@ -2,19 +2,25 @@

// RUN: %clang_cc1 -triple powerpc64le-unknown-linux-gnu -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64-unknown-linux-gnu -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -triple powerpc64-ibm-aix -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s
// RUN: %clang_cc1 -triple powerpc-ibm-aix -target-feature +vsx \
// RUN: -target-cpu pwr9 -emit-llvm %s -o - | FileCheck %s

// This case is to test VSX register support in the clobbers list for inline asm.
void testVSX (void) {
unsigned int a = 0;
unsigned int *dbell=&a;
int d;
__asm__ __volatile__ (
"lxvw4x %%vs32, 0, %2\n\t"
"stxvw4x %%vs32, 0, %1"
"lxvw4x 32, 0, %2\n\t"
"stxvw4x 32, 0, %1"
: "=m"(*(volatile unsigned int*)(dbell))
: "r" (dbell), "r" (&d)
: "vs32"
);
}

// CHECK: call void asm sideeffect "lxvw4x %vs32, 0, $2\0A\09stxvw4x %vs32, 0, $1", "=*m,r,r,~{vs32}"
// CHECK: call void asm sideeffect "lxvw4x 32, 0, $2\0A\09stxvw4x 32, 0, $1", "=*m,r,r,~{vs32}"