KVM: PPC: Book3S HV: Sanitize special-purpose register values on guest exit

jira LE-1907
Rebuild_History Non-Buildable kernel-3.10.0-514.el7
Rebuild_CHGLOG: - [powerpc] kvm: book3s_hv: Sanitize special-purpose register values on guest exit (Thomas Huth) [1313725]
Rebuild_FUZZ: 95.17%
commit-author Paul Mackerras <[email protected]>
commit ccec445

Thomas Huth discovered that a guest could cause a hard hang of a
host CPU by setting the Instruction Authority Mask Register (IAMR)
to a suitable value.  It turns out that this is because when the
code was added to context-switch the new special-purpose registers
(SPRs) that were added in POWER8, we forgot to add code to ensure
that they were restored to a sane value on guest exit.

This adds code to set those registers where a bad value could
compromise the execution of the host kernel to a suitable neutral
value on guest exit.

	Cc: [email protected] # v3.14+
Fixes: b005255
	Reported-by: Thomas Huth <[email protected]>
	Reviewed-by: David Gibson <[email protected]>
	Signed-off-by: Paul Mackerras <[email protected]>
(cherry picked from commit ccec445)
	Signed-off-by: Jonathan Maple <[email protected]>

Author: PlaidCat

arch/powerpc/kvm/book3s_hv_rmhandlers.S

@@ -1458,6 +1458,20 @@ END_FTR_SECTION_IFCLR(CPU_FTR_ARCH_207S)
 	std	r6, VCPU_ACOP(r9)
 	stw	r7, VCPU_GUEST_PID(r9)
 	std	r8, VCPU_WORT(r9)
+	/*
+	 * Restore various registers to 0, where non-zero values
+	 * set by the guest could disrupt the host.
+	 */
+	li	r0, 0
+	mtspr	SPRN_IAMR, r0
+	mtspr	SPRN_CIABR, r0
+	mtspr	SPRN_DAWRX, r0
+	mtspr	SPRN_TCSCR, r0
+	mtspr	SPRN_WORT, r0
+	/* Set MMCRS to 1<<31 to freeze and disable the SPMC counters */
+	li	r0, 1
+	sldi	r0, r0, 31
+	mtspr	SPRN_MMCRS, r0
 8:
 
 	/* Save and reset AMR and UAMOR before turning on the MMU */