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Revert "Update SoC FPGA hwmon documentation and devicetrees (#3)" (#4)
This reverts commit 92991a0.
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‎Documentation/devicetree/bindings/hwmon/intel,soc64-hwmon.yaml‎

Lines changed: 13 additions & 112 deletions
Original file line numberDiff line numberDiff line change
@@ -10,129 +10,30 @@ maintainers:
1010
- Ang Tien Sung <[email protected]>
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description: |
13-
The Intel SoC FPGA hardware monitor unit provides on-chip voltage and
14-
temperature sensors. You can use these sensors to monitor external
15-
voltages and on-chip operating conditions such as internal power rails
16-
and on-chip junction temperatures.
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18-
The specific sensor configurations vary for each device family and
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each device within a family does not offer all potential sensor
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options. The information below attempts to illustrate the super set of
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possible sensor options that are potentially available within each
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device family, but the user should check the documentation for the
23-
specific device they are using to verify which sensor options it
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actually provides.
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Stratix 10 Device Family
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Stratix 10 Voltage Sensors
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page 0, channel 2 = 0.8V VCC
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page 0, channel 3 = 1.0V VCCIO
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page 0, channel 6 = 0.9V VCCERAM
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34-
Stratix 10 Temperature Sensors
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page 0, channel 0 = main die
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page 0, channel 1 = tile bottom left
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page 0, channel 2 = tile middle left
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page 0, channel 3 = tile top left
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page 0, channel 4 = tile bottom right
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page 0, channel 5 = tile middle right
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page 0, channel 6 = tile top right
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page 0, channel 7 = hbm2 bottom
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page 0, channel 8 = hbm2 top
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46-
Agilex Device Family
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Agilex Voltage Sensors
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50-
page 0, channel 2 = 0.8V VCC
51-
page 0, channel 3 = 1.8V VCCIO_SDM
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page 0, channel 4 = 1.8V VCCPT
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page 0, channel 5 = 1.2V VCCRCORE
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page 0, channel 6 = 0.9V VCCH
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page 0, channel 7 = 0.8V VCCL
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57-
Agilex Temperature Sensors
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page 0, channel 0 = main die sdm max
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page 0, channel 1 = main die sdm 1
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62-
page 1, channel 0 = main die corner bottom left max
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page 1, channel 1 = main die corner bottom left 1
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page 1, channel 2 = main die corner bottom left 2
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66-
page 2, channel 0 = main die corner top left max
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page 2, channel 1 = main die corner top left 1
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page 2, channel 2 = main die corner top left 2
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70-
page 3, channel 0 = main die corner bottom right max
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page 3, channel 1 = main die corner bottom right 1
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page 3, channel 2 = main die corner bottom right 2
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page 4, channel 0 = main die corner top right max
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page 4, channel 1 = main die corner top right 1
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page 4, channel 2 = main die corner top right 2
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78-
page 5, channel 0 = tile die bottom left max
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page 5, channel 1 = tile die bottom left 1
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page 5, channel 6..2 = tile die bottom left 6..2 R-tile only
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page 5, channel 5..2 = tile die bottom left 5..2 F-tile only
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page 5, channel 4..2 = tile die bottom left 4..2 E-tile only
83-
84-
page 7, channel 0 = tile die top left max
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page 7, channel 1 = tile die top left 1
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page 7, channel 6..2 = tile die top left 6..2 R-tile only
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page 7, channel 5..2 = tile die top left 5..2 F-tile only
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page 7, channel 4..2 = tile die top left 4..2 E-tile only
89-
90-
page 8, channel 0 = tile die bottom right max
91-
page 8, channel 1 = tile die bottom right 1
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page 8, channel 6..2 = tile die bottom right 6..2 R-tile only
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page 8, channel 5..2 = tile die bottom right 5..2 F-tile only
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page 8, channel 4..2 = tile die bottom right 4..2 E-tile only
95-
96-
page 10, channel 0 = tile die top right max
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page 10, channel 1 = tile die top right 1
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page 10, channel 6..2 = tile die top right 6..2 R-tile only
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page 10, channel 5..2 = tile die top right 5..2 F-tile only
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page 10, channel 4..2 = tile die top right 4..2 E-tile only
101-
102-
N5X Device Family
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N5X Voltage Sensors
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page 0, channel 2 = 0.8V VDD
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page 0, channel 3 = 0.8V VDD_SDM
108-
page 0, channel 4 = 1.8V VCCADC
109-
page 0, channel 5 = 1.8V VCCPD
110-
page 0, channel 6 = 1.8V VCCIO_SDM
111-
page 0, channel 7 = 0.8V VDD_HPS
112-
113-
N5X Temperature Sensors
114-
115-
page 0, channel 0 = main die
13+
This is the Intel SoC FPGA hardware monitor unit provides you with
14+
on-chip voltage and temperature sensors. You can use these sensors
15+
to monitor external voltages and on-chip operation conditions such
16+
as internal power rail and on-chip junction temperature.
11617
11718
properties:
11819
compatible: "intel,soc64-hwmon"
11920
temperature:
12021
description:
12122
Specifies the possible mappings of temperature sensors
122-
diodes on the SOC FPGA main die and tile die.
23+
diodes on the SOC FPGA main die.
12324
voltage:
12425
description:
125-
Specifies the possible mappings of the voltage sensors on the
126-
SOC FPGA analog to digital converter of the Secure Device Manager
127-
(SDM).
26+
Specifies the possible mappings of the voltage sensors
27+
on the SOC FPGA analog to digital converter of the secure device
28+
manager (SDM).
12829
input:
12930
description:
13031
Specifies each sensor.
13132
reg:
13233
description:
133-
The sensor mapping address is denoted by the lower 16-bits being
34+
The sensor mapping address denoted by lower 16bits being
13435
the channel mask location that defines the channel number.
135-
The upper 16-bits denotes the page number.
36+
The upper 16bits denotes the page number.
13637
The bit mask of 0x1 represents channel 1. The supported
13738
page and channel is dependent on the SOC FPGA variant.
13839
Page number greater than 0 is only supported on the
@@ -198,7 +99,7 @@ examples:
19899
};
199100
200101
input@10002 {
201-
label = "Main Die corner bottom left 2";
102+
label = "Main Die corner bottom left 1";
202103
reg = <0x10002>;
203104
};
204105
@@ -223,12 +124,12 @@ examples:
223124
};
224125
225126
input@40001 {
226-
label = "Main Die corner top right 1 HPS";
127+
label = "Main Die corner top right HPS 1";
227128
reg = <0x40001>;
228129
};
229130
230131
input@40002 {
231-
label = "Main Die corner top right 2";
132+
label = "Main Die corner bottom right";
232133
reg = <0x40002>;
233134
};
234135
};

‎arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts‎

Lines changed: 32 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -109,24 +109,44 @@
109109
reg = <0x0>;
110110
};
111111

112-
input@10000 {
113-
label = "Main Die corner bottom left max";
114-
reg = <0x10000>;
112+
input@10001 {
113+
label = "Main Die corner bottom left 1";
114+
reg = <0x10001>;
115115
};
116116

117-
input@20000 {
118-
label = "Main Die corner top left max";
119-
reg = <0x20000>;
117+
input@10002 {
118+
label = "Main Die corner bottom left 1";
119+
reg = <0x10002>;
120120
};
121121

122-
input@30000 {
123-
label = "Main Die corner bottom right max";
124-
reg = <0x30000>;
122+
input@20001 {
123+
label = "Main Die corner top left 1";
124+
reg = <0x20001>;
125125
};
126126

127-
input@40000 {
128-
label = "Main Die corner top right max";
129-
reg = <0x40000>;
127+
input@20002 {
128+
label = "Main Die corner top left 2";
129+
reg = <0x20002>;
130+
};
131+
132+
input@30001 {
133+
label = "Main Die corner bottom right 1";
134+
reg = <0x30001>;
135+
};
136+
137+
input@30002 {
138+
label = "Main Die corner bottom right 2";
139+
reg = <0x30002>;
140+
};
141+
142+
input@40001 {
143+
label = "Main Die corner top right HPS 1";
144+
reg = <0x40001>;
145+
};
146+
147+
input@40002 {
148+
label = "Main Die corner bottom right";
149+
reg = <0x40002>;
130150
};
131151
};
132152
};

‎arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts‎

Lines changed: 32 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -181,24 +181,44 @@
181181
reg = <0x0>;
182182
};
183183

184-
input@10000 {
185-
label = "Main Die corner bottom left max";
186-
reg = <0x10000>;
184+
input@10001 {
185+
label = "Main Die corner bottom left 1";
186+
reg = <0x10001>;
187187
};
188188

189-
input@20000 {
190-
label = "Main Die corner top left max";
191-
reg = <0x20000>;
189+
input@10002 {
190+
label = "Main Die corner bottom left 1";
191+
reg = <0x10002>;
192192
};
193193

194-
input@30000 {
195-
label = "Main Die corner bottom right max";
196-
reg = <0x30000>;
194+
input@20001 {
195+
label = "Main Die corner top left 1";
196+
reg = <0x20001>;
197197
};
198198

199-
input@40000 {
200-
label = "Main Die corner top right max";
201-
reg = <0x40000>;
199+
input@20002 {
200+
label = "Main Die corner top left 2";
201+
reg = <0x20002>;
202+
};
203+
204+
input@30001 {
205+
label = "Main Die corner bottom right 1";
206+
reg = <0x30001>;
207+
};
208+
209+
input@30002 {
210+
label = "Main Die corner bottom right 2";
211+
reg = <0x30002>;
212+
};
213+
214+
input@40001 {
215+
label = "Main Die corner top right HPS 1";
216+
reg = <0x40001>;
217+
};
218+
219+
input@40002 {
220+
label = "Main Die corner bottom right";
221+
reg = <0x40002>;
202222
};
203223
};
204224
};

‎arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts‎

Lines changed: 32 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -158,24 +158,44 @@
158158
reg = <0x0>;
159159
};
160160

161-
input@10000 {
162-
label = "Main Die corner bottom left max";
163-
reg = <0x10000>;
161+
input@10001 {
162+
label = "Main Die corner bottom left 1";
163+
reg = <0x10001>;
164164
};
165165

166-
input@20000 {
167-
label = "Main Die corner top left max";
168-
reg = <0x20000>;
166+
input@10002 {
167+
label = "Main Die corner bottom left 1";
168+
reg = <0x10002>;
169169
};
170170

171-
input@30000 {
172-
label = "Main Die corner bottom right max";
173-
reg = <0x30000>;
171+
input@20001 {
172+
label = "Main Die corner top left 1";
173+
reg = <0x20001>;
174174
};
175175

176-
input@40000 {
177-
label = "Main Die corner top right max";
178-
reg = <0x40000>;
176+
input@20002 {
177+
label = "Main Die corner top left 2";
178+
reg = <0x20002>;
179+
};
180+
181+
input@30001 {
182+
label = "Main Die corner bottom right 1";
183+
reg = <0x30001>;
184+
};
185+
186+
input@30002 {
187+
label = "Main Die corner bottom right 2";
188+
reg = <0x30002>;
189+
};
190+
191+
input@40001 {
192+
label = "Main Die corner top right HPS 1";
193+
reg = <0x40001>;
194+
};
195+
196+
input@40002 {
197+
label = "Main Die corner bottom right";
198+
reg = <0x40002>;
179199
};
180200
};
181201
};

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