Skip to content

Commit 92991a0

Browse files
rodfrazer-intelrodfrazer-intel
authored
Update SoC FPGA hwmon documentation and devicetrees (#3)
* Update SoC FPGA hwmon documentation and devicetrees - Documentation/devicetree/bindings/hwmon/intel,soc64-hwmon.yaml Add additional details about the potential sensor locations available in each device family. - arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts - arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts - arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts Modify the example temperature sensor locations to demonstrate the maximum temperature value rather than the individual diode values. - arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts Modify the example temperature sensor locations to demonstrate only the main die sensor. This device family does not appear to implement any other temperature sensors. Signed-off-by: Rod Frazer <[email protected]> * Update N5X hwmon documentation and devicetrees - Documentation/devicetree/bindings/hwmon/intel,soc64-hwmon.yaml Update the Voltage Monitor descriptions for the N5X device to align with the descriptions from the N5X documentation. - arch/arm64/boot/dts/intel/socfpga_n5x_socdk.dts Update the Voltage Monitor labels for the N5X device to align with the descriptions from the N5X documentation. Signed-off-by: Rod Frazer <[email protected]> Signed-off-by: Rod Frazer <[email protected]>
1 parent b3737d7 commit 92991a0

File tree

5 files changed

+154
-155
lines changed

5 files changed

+154
-155
lines changed

‎Documentation/devicetree/bindings/hwmon/intel,soc64-hwmon.yaml‎

Lines changed: 112 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -10,30 +10,129 @@ maintainers:
1010
- Ang Tien Sung <[email protected]>
1111

1212
description: |
13-
This is the Intel SoC FPGA hardware monitor unit provides you with
14-
on-chip voltage and temperature sensors. You can use these sensors
15-
to monitor external voltages and on-chip operation conditions such
16-
as internal power rail and on-chip junction temperature.
13+
The Intel SoC FPGA hardware monitor unit provides on-chip voltage and
14+
temperature sensors. You can use these sensors to monitor external
15+
voltages and on-chip operating conditions such as internal power rails
16+
and on-chip junction temperatures.
17+
18+
The specific sensor configurations vary for each device family and
19+
each device within a family does not offer all potential sensor
20+
options. The information below attempts to illustrate the super set of
21+
possible sensor options that are potentially available within each
22+
device family, but the user should check the documentation for the
23+
specific device they are using to verify which sensor options it
24+
actually provides.
25+
26+
Stratix 10 Device Family
27+
28+
Stratix 10 Voltage Sensors
29+
30+
page 0, channel 2 = 0.8V VCC
31+
page 0, channel 3 = 1.0V VCCIO
32+
page 0, channel 6 = 0.9V VCCERAM
33+
34+
Stratix 10 Temperature Sensors
35+
36+
page 0, channel 0 = main die
37+
page 0, channel 1 = tile bottom left
38+
page 0, channel 2 = tile middle left
39+
page 0, channel 3 = tile top left
40+
page 0, channel 4 = tile bottom right
41+
page 0, channel 5 = tile middle right
42+
page 0, channel 6 = tile top right
43+
page 0, channel 7 = hbm2 bottom
44+
page 0, channel 8 = hbm2 top
45+
46+
Agilex Device Family
47+
48+
Agilex Voltage Sensors
49+
50+
page 0, channel 2 = 0.8V VCC
51+
page 0, channel 3 = 1.8V VCCIO_SDM
52+
page 0, channel 4 = 1.8V VCCPT
53+
page 0, channel 5 = 1.2V VCCRCORE
54+
page 0, channel 6 = 0.9V VCCH
55+
page 0, channel 7 = 0.8V VCCL
56+
57+
Agilex Temperature Sensors
58+
59+
page 0, channel 0 = main die sdm max
60+
page 0, channel 1 = main die sdm 1
61+
62+
page 1, channel 0 = main die corner bottom left max
63+
page 1, channel 1 = main die corner bottom left 1
64+
page 1, channel 2 = main die corner bottom left 2
65+
66+
page 2, channel 0 = main die corner top left max
67+
page 2, channel 1 = main die corner top left 1
68+
page 2, channel 2 = main die corner top left 2
69+
70+
page 3, channel 0 = main die corner bottom right max
71+
page 3, channel 1 = main die corner bottom right 1
72+
page 3, channel 2 = main die corner bottom right 2
73+
74+
page 4, channel 0 = main die corner top right max
75+
page 4, channel 1 = main die corner top right 1
76+
page 4, channel 2 = main die corner top right 2
77+
78+
page 5, channel 0 = tile die bottom left max
79+
page 5, channel 1 = tile die bottom left 1
80+
page 5, channel 6..2 = tile die bottom left 6..2 R-tile only
81+
page 5, channel 5..2 = tile die bottom left 5..2 F-tile only
82+
page 5, channel 4..2 = tile die bottom left 4..2 E-tile only
83+
84+
page 7, channel 0 = tile die top left max
85+
page 7, channel 1 = tile die top left 1
86+
page 7, channel 6..2 = tile die top left 6..2 R-tile only
87+
page 7, channel 5..2 = tile die top left 5..2 F-tile only
88+
page 7, channel 4..2 = tile die top left 4..2 E-tile only
89+
90+
page 8, channel 0 = tile die bottom right max
91+
page 8, channel 1 = tile die bottom right 1
92+
page 8, channel 6..2 = tile die bottom right 6..2 R-tile only
93+
page 8, channel 5..2 = tile die bottom right 5..2 F-tile only
94+
page 8, channel 4..2 = tile die bottom right 4..2 E-tile only
95+
96+
page 10, channel 0 = tile die top right max
97+
page 10, channel 1 = tile die top right 1
98+
page 10, channel 6..2 = tile die top right 6..2 R-tile only
99+
page 10, channel 5..2 = tile die top right 5..2 F-tile only
100+
page 10, channel 4..2 = tile die top right 4..2 E-tile only
101+
102+
N5X Device Family
103+
104+
N5X Voltage Sensors
105+
106+
page 0, channel 2 = 0.8V VDD
107+
page 0, channel 3 = 0.8V VDD_SDM
108+
page 0, channel 4 = 1.8V VCCADC
109+
page 0, channel 5 = 1.8V VCCPD
110+
page 0, channel 6 = 1.8V VCCIO_SDM
111+
page 0, channel 7 = 0.8V VDD_HPS
112+
113+
N5X Temperature Sensors
114+
115+
page 0, channel 0 = main die
17116
18117
properties:
19118
compatible: "intel,soc64-hwmon"
20119
temperature:
21120
description:
22121
Specifies the possible mappings of temperature sensors
23-
diodes on the SOC FPGA main die.
122+
diodes on the SOC FPGA main die and tile die.
24123
voltage:
25124
description:
26-
Specifies the possible mappings of the voltage sensors
27-
on the SOC FPGA analog to digital converter of the secure device
28-
manager (SDM).
125+
Specifies the possible mappings of the voltage sensors on the
126+
SOC FPGA analog to digital converter of the Secure Device Manager
127+
(SDM).
29128
input:
30129
description:
31130
Specifies each sensor.
32131
reg:
33132
description:
34-
The sensor mapping address denoted by lower 16bits being
133+
The sensor mapping address is denoted by the lower 16-bits being
35134
the channel mask location that defines the channel number.
36-
The upper 16bits denotes the page number.
135+
The upper 16-bits denotes the page number.
37136
The bit mask of 0x1 represents channel 1. The supported
38137
page and channel is dependent on the SOC FPGA variant.
39138
Page number greater than 0 is only supported on the
@@ -99,7 +198,7 @@ examples:
99198
};
100199
101200
input@10002 {
102-
label = "Main Die corner bottom left 1";
201+
label = "Main Die corner bottom left 2";
103202
reg = <0x10002>;
104203
};
105204
@@ -124,12 +223,12 @@ examples:
124223
};
125224
126225
input@40001 {
127-
label = "Main Die corner top right HPS 1";
226+
label = "Main Die corner top right 1 HPS";
128227
reg = <0x40001>;
129228
};
130229
131230
input@40002 {
132-
label = "Main Die corner bottom right";
231+
label = "Main Die corner top right 2";
133232
reg = <0x40002>;
134233
};
135234
};

‎arch/arm64/boot/dts/intel/socfpga_agilex_n6000.dts‎

Lines changed: 12 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -109,44 +109,24 @@
109109
reg = <0x0>;
110110
};
111111

112-
input@10001 {
113-
label = "Main Die corner bottom left 1";
114-
reg = <0x10001>;
112+
input@10000 {
113+
label = "Main Die corner bottom left max";
114+
reg = <0x10000>;
115115
};
116116

117-
input@10002 {
118-
label = "Main Die corner bottom left 1";
119-
reg = <0x10002>;
117+
input@20000 {
118+
label = "Main Die corner top left max";
119+
reg = <0x20000>;
120120
};
121121

122-
input@20001 {
123-
label = "Main Die corner top left 1";
124-
reg = <0x20001>;
122+
input@30000 {
123+
label = "Main Die corner bottom right max";
124+
reg = <0x30000>;
125125
};
126126

127-
input@20002 {
128-
label = "Main Die corner top left 2";
129-
reg = <0x20002>;
130-
};
131-
132-
input@30001 {
133-
label = "Main Die corner bottom right 1";
134-
reg = <0x30001>;
135-
};
136-
137-
input@30002 {
138-
label = "Main Die corner bottom right 2";
139-
reg = <0x30002>;
140-
};
141-
142-
input@40001 {
143-
label = "Main Die corner top right HPS 1";
144-
reg = <0x40001>;
145-
};
146-
147-
input@40002 {
148-
label = "Main Die corner bottom right";
149-
reg = <0x40002>;
127+
input@40000 {
128+
label = "Main Die corner top right max";
129+
reg = <0x40000>;
150130
};
151131
};
152132
};

‎arch/arm64/boot/dts/intel/socfpga_agilex_socdk.dts‎

Lines changed: 12 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -181,44 +181,24 @@
181181
reg = <0x0>;
182182
};
183183

184-
input@10001 {
185-
label = "Main Die corner bottom left 1";
186-
reg = <0x10001>;
184+
input@10000 {
185+
label = "Main Die corner bottom left max";
186+
reg = <0x10000>;
187187
};
188188

189-
input@10002 {
190-
label = "Main Die corner bottom left 1";
191-
reg = <0x10002>;
189+
input@20000 {
190+
label = "Main Die corner top left max";
191+
reg = <0x20000>;
192192
};
193193

194-
input@20001 {
195-
label = "Main Die corner top left 1";
196-
reg = <0x20001>;
194+
input@30000 {
195+
label = "Main Die corner bottom right max";
196+
reg = <0x30000>;
197197
};
198198

199-
input@20002 {
200-
label = "Main Die corner top left 2";
201-
reg = <0x20002>;
202-
};
203-
204-
input@30001 {
205-
label = "Main Die corner bottom right 1";
206-
reg = <0x30001>;
207-
};
208-
209-
input@30002 {
210-
label = "Main Die corner bottom right 2";
211-
reg = <0x30002>;
212-
};
213-
214-
input@40001 {
215-
label = "Main Die corner top right HPS 1";
216-
reg = <0x40001>;
217-
};
218-
219-
input@40002 {
220-
label = "Main Die corner bottom right";
221-
reg = <0x40002>;
199+
input@40000 {
200+
label = "Main Die corner top right max";
201+
reg = <0x40000>;
222202
};
223203
};
224204
};

‎arch/arm64/boot/dts/intel/socfpga_agilex_socdk_nand.dts‎

Lines changed: 12 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -158,44 +158,24 @@
158158
reg = <0x0>;
159159
};
160160

161-
input@10001 {
162-
label = "Main Die corner bottom left 1";
163-
reg = <0x10001>;
161+
input@10000 {
162+
label = "Main Die corner bottom left max";
163+
reg = <0x10000>;
164164
};
165165

166-
input@10002 {
167-
label = "Main Die corner bottom left 1";
168-
reg = <0x10002>;
166+
input@20000 {
167+
label = "Main Die corner top left max";
168+
reg = <0x20000>;
169169
};
170170

171-
input@20001 {
172-
label = "Main Die corner top left 1";
173-
reg = <0x20001>;
171+
input@30000 {
172+
label = "Main Die corner bottom right max";
173+
reg = <0x30000>;
174174
};
175175

176-
input@20002 {
177-
label = "Main Die corner top left 2";
178-
reg = <0x20002>;
179-
};
180-
181-
input@30001 {
182-
label = "Main Die corner bottom right 1";
183-
reg = <0x30001>;
184-
};
185-
186-
input@30002 {
187-
label = "Main Die corner bottom right 2";
188-
reg = <0x30002>;
189-
};
190-
191-
input@40001 {
192-
label = "Main Die corner top right HPS 1";
193-
reg = <0x40001>;
194-
};
195-
196-
input@40002 {
197-
label = "Main Die corner bottom right";
198-
reg = <0x40002>;
176+
input@40000 {
177+
label = "Main Die corner top right max";
178+
reg = <0x40000>;
199179
};
200180
};
201181
};

0 commit comments

Comments
 (0)