more RISC-V backend progress #20474
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more RISC-V backend progress #20474
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Now we generate debug undefined constants when the user asks for them to dedup across the function decl. This takes 2 instructions instead of 7 in the RISC-V backend. TODO, we need to dedupe across function decl boundaries.
* the file's doc-comment was misleading and did not focus on the correct aspect of SIMD * added cpu flag awareness to `suggestVectorLengthForCpu` in order to provide a more accurate vector length
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@atomicLoad,@atomicStore,@atomicRmw,@fencestd.simd.suggestVectorLengthmore accurate for RISC-V1297 passed, 639 failed - 66.99% passingcc @kubkon