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aarch64 llvm 14 regression with vectors: assertion `TmpVec.size() > 1' failed #12012

@andrewrk

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@andrewrk

Zig Version: 0.10.0-dev.2876+fbd6c8832

This test case regressed with the update from LLVM 13 to 14:

test "tuple to vector" {
    const S = struct {
        fn doTheTest() !void {
            const Vec3 = @Vector(3, i32);
            var v: Vec3 = .{ 1, 0, 0 };
            for ([_]Vec3{ .{ 0, 1, 0 }, .{ 0, 0, 1 } }) |it| {
                v += it;
            }

            try std.testing.expectEqual(v, Vec3{ 1, 1, 1 });
            if (builtin.zig_backend != .stage1) {
                try std.testing.expectEqual(v, .{ 1, 1, 1 });
            }
        }
    };
    try S.doTheTest();
    comptime try S.doTheTest();
}
[nix-shell:~/dev/zig/build-llvm14-debug]$ stage1/bin/zig cc test.ll -target aarch64-linux-none
zig: /home/andy/Downloads/llvm-project-14/llvm/lib/CodeGen/GlobalISel/MachineIRBuilder.cpp:656: llvm::MachineInstrBuilder llvm::MachineIRBuilder::buildUnmerge(llvm::ArrayRef<llvm::Register>, const llvm::SrcOp&): Assertion `TmpVec.size() > 1' failed.

Reduced LLVM IR:

define internal fastcc i16 @test2.doTheTest.S.doTheTest() {
Block10:
  %0 = call fastcc i16 undef(<3 x i32> zeroinitializer, <3 x i32> zeroinitializer)
  ret i16 0
}

Upstream bug report: llvm/llvm-project#56397

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    arch-aarch6464-bit Armbackend-llvmThe LLVM backend outputs an LLVM IR Module.bugObserved behavior contradicts documented or intended behaviorcontributor friendlyThis issue is limited in scope and/or knowledge of Zig internals.upstreamAn issue with a third party project that Zig uses.

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