[WIP] uhc_dwc2: Initial support for nRF54LM20-DK

[josuah]

Dependencies:

• drivers: uhc_dwc2: Initial support [WIP] #94266

This is an extremely early state and not expected to work so far.

There is only some work on the PHY and import of nRF54LM20 device driver (UDC) vendor quirks on top of the PR #94266.

west build -t flash -b nrf54lm20dk/nrf54lm20a/cpuapp samples/subsys/usb/shell/ \
  -DEXTRA_CONF_FILE=host_prj.conf \
  -DCONFIG_USB_DEVICE_STACK_NEXT=n \
  -DCONFIG_UHC_DRIVER_LOG_LEVEL_DBG=y

To test:

$ picocom -b 115200 /dev/ttyACM1

Then on the shell:

*** Booting Zephyr OS build v4.2.0-500-gbceea0081030 ***
uart:~$ usbh init 
host: USB host initialized
uart:~$ usbh enable 
host: USB host enabled
[00:00:14.452,032] <dbg> uhc_dwc2: dwc2_hal_get_config: GSNPSID=4F54500Bh, GHWCFG2=22AFFC52h, GHWCFG3=0BE0C0E8h, GHWCFG4=3E10AA60h
[00:00:14.452,046] <dbg> uhc_dwc2: dwc2_hal_get_config: Buffer DMA enabled
[00:00:14.452,052] <dbg> uhc_dwc2: dwc2_hal_get_config: Dynamic FIFO Sizing is enabled
[00:00:14.452,058] <dbg> uhc_dwc2: dwc2_hal_get_config: OTG architecture (OTGARCH) 2, mode (OTGMODE) 2
[00:00:14.452,065] <dbg> uhc_dwc2: dwc2_hal_get_config: DFIFO depth (DFIFODEPTH) 12160 bytes
[00:00:14.452,094] <dbg> uhc_dwc2: dwc2_hal_get_config: Vendor Control interface support enabled: false
[00:00:14.452,102] <dbg> uhc_dwc2: dwc2_hal_get_config: PHY interface type: FSPHYTYPE 0, HSPHYTYPE 1, DATAWIDTH 2
[00:00:14.452,114] <dbg> uhc_dwc2: dwc2_hal_get_config: LPM mode is enabled
[00:00:14.452,122] <dbg> uhc_dwc2: dwc2_hal_get_config: PHY interface type: FSPHYTYPE 0, HSPHYTYPE 1, DATAWIDTH 2
[00:00:14.452,128] <dbg> uhc_dwc2: dwc2_hal_get_config: Number of host channels (NUMHSTCHNL + 1) 16
[00:00:14.452,139] <dbg> uhc_dwc2: uhc_dwc2_config_fifo_fixed_dma: Configuring FIFO sizes
[00:00:14.452,146] <dbg> uhc_dwc2: uhc_dwc2_config_fifo_fixed_dma: FIFO sizes calculated
[00:00:14.452,153] <dbg> uhc_dwc2: uhc_dwc2_config_fifo_fixed_dma: 	top=12096, nptx=128, rx=592, ptx=11376
[00:00:14.452,159] <wrn> uhc_dwc2: Highspeed UTMI+ PHY init
[00:00:14.452,169] <dbg> uhc_dwc2: dwc2_hal_core_reset: DWC2 core reset done
[00:00:14.492,599] <dbg> uhc_dwc2: uhc_dwc2_decode_intr: GINTSTS=14008C24h, HPRT=00000000h
uart:~$ 

Then plug/unplug an USB device while powering the VBUS externally (i.e. charger/data adapter and an USB dongle), and observe interrupts arriving:

uart:~$ 
[00:00:16.090,156] <dbg> uhc_dwc2: uhc_dwc2_decode_intr: GINTSTS=04801024h, HPRT=00000000h
[00:00:17.484,624] <dbg> uhc_dwc2: uhc_dwc2_decode_intr: GINTSTS=04002024h, HPRT=00000000h
[00:00:17.490,753] <dbg> uhc_dwc2: uhc_dwc2_decode_intr: GINTSTS=04008C24h, HPRT=00000000h
uart:~$ 

For now this is all it does.

Next on the roadmap is to get interrupts working while running in host mode and verify the chain of registers matches what is on the databook, to try to get an USB device detected on the bus.

[josuah]

Removing all reviewers until this makes sense to look at the content.
I will work on a _wip branch in the meantime to reduce notification spam.

[josuah]

I noticed the DK has VBUS which is the "system 5V rail" rather than the VBUS provided to the device as part of the 4 USB pins [GND, VBUS, D+, D-] (of course more in Type-C).

The VBUS provided to the device, probed at TP21, stays near 0V and I suspect I need to read the PHY doc more.

I will look further how to control this.

[sonarqubecloud]

Quality Gate passed

Issues
2 New issues
0 Accepted issues

Measures
0 Security Hotspots
0.0% Coverage on New Code
0.0% Duplication on New Code

See analysis details on SonarQube Cloud

[josuah]

I just realized I already opened that in #95723 so closing this one.