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@VynDragon VynDragon commented Sep 28, 2025

Introduce flash driver for 1 bank of flash (all of them on bl60x and bl70x, half of them on bl61x)

Caveat: no bank2 support (feature of bl61x)
Not sure how to handle the flash naming and devices as they are either separate die flash or external flash but need the controller to work (and so be soc-nv-flash).

@VynDragon VynDragon requested a review from josuah September 28, 2025 15:33
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github-actions bot commented Sep 28, 2025

The following west manifest projects have changed revision in this Pull Request:

Name Old Revision New Revision Diff

All manifest checks OK

Note: This message is automatically posted and updated by the Manifest GitHub Action.

@github-actions github-actions bot added manifest manifest-hal_bouffalolab DNM (manifest) This PR should not be merged (controlled by action-manifest) labels Sep 28, 2025
@VynDragon VynDragon added area: Flash platform: Bouffalo Lab and removed manifest manifest-hal_bouffalolab DNM (manifest) This PR should not be merged (controlled by action-manifest) labels Sep 28, 2025
@github-actions github-actions bot added manifest manifest-hal_bouffalolab DNM (manifest) This PR should not be merged (controlled by action-manifest) labels Sep 28, 2025
@VynDragon VynDragon force-pushed the bflb_flash_work branch 3 times, most recently from 5db0053 to 2a4c5d9 Compare October 10, 2025 18:46
@VynDragon VynDragon marked this pull request as ready for review October 10, 2025 18:50
@zephyrbot zephyrbot added area: Boards/SoCs area: RISCV RISCV Architecture (32-bit & 64-bit) labels Oct 10, 2025
@VynDragon VynDragon requested a review from josuah October 24, 2025 10:46
@github-actions github-actions bot removed manifest manifest-hal_bouffalolab DNM (manifest) This PR should not be merged (controlled by action-manifest) labels Oct 24, 2025
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@de-nordic PTAL? Thanks.

josuah
josuah previously approved these changes Oct 24, 2025
Comment on lines 1093 to 1095
if (length == 0) {
return 0;
}
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In all cases, lack of action should not generate an error. This means the length check should go above range check.

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done

Comment on lines 272 to 279
if (offset < 0) {
LOG_WRN("0x%lx: before start of flash", (long)offset);
return -EINVAL;
}
if ((offset + len) > TOTAL_SIZE) {
LOG_WRN("0x%lx: ends past the end of flash", (long)offset);
return -EINVAL;
}
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No need to separate checks, imho.
The check should be:

offset < 0 || len > TOTAL_SIZE || ((TOTAL_SIZE - offset) < len)

above avoids integer overflows.

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Separated errors for different problems however, are useful. Done

return ret;
}

if (len == 0) {
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Len check above range valid check.

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Sorry, counted 3, forgetting there's 2 different read... Done

josuah
josuah previously approved these changes Oct 24, 2025
@VynDragon VynDragon modified the milestones: v4.3.0, v4.4.0 Nov 5, 2025
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@de-nordic PTAL

static bool flash_bflb_is_in_xip(void *func)
{
if ((uint32_t)func > BFLB_XIP_BASE && (uint32_t)func < BFLB_XIP_END) {
LOG_ERR("function at %d is in XIP and will crash the device", (uint32_t)func);
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You probably want to use %p instead of %d and avoid casting the func.

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done


#if defined(CONFIG_SOC_SERIES_BL70X) || defined(CONFIG_SOC_SERIES_BL60X)

static void flash_bflb_l1c_wrap(bool yes)
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Not my driver, but yes for a bool variable is not descriptive of the purpose.

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it's the same as 'writing?' yes/no, l1c_wrap? yes/no

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done


static void flash_bflb_l1c_wrap(bool yes)
{
/* Do nothing on Bl61x: no L1C */
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You will probably get here unused variable warning from static analysis, so it would be good to have ARG_UNUSED(yes) here

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done

Comment on lines 383 to 389
if (data_mode == 0) {
return 0;
} else if (data_mode == 1) {
return 1;
} else if (data_mode == 2) {
return 2;
}
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You can just return data_mode here.
Shouldn't be here some asserts, for validation builds, to check if only values covered by ifs are processed?

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done

tmp &= ~SF_CTRL_SF_IF_0_DAT_EN_MSK;
}

/* writing ? */
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I do not know. Are we?

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done

erase_cmd.rw = 0;
erase_cmd.addr_size = 3;

for (uint32_t i = start / ERASE_SIZE; i < ((len / ERASE_SIZE) + start / ERASE_SIZE); i++) {
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On some CPUs it is better avoid division when possible, and this loop will have at least two of these every run, if fail to optimize. Consider pre calculating loop-independent ending condition before defining loop.

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This only runs on CPUs that are fine with that and all have FPUs as well, will add the precalculations however.

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done

Comment on lines 1342 to 1349
ret = flash_bflb_restore_xip_state(data);
irq_unlock(locker);

return ret;

exit_here:
flash_bflb_restore_xip_state(data);
irq_unlock(locker);
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Same as flash_bflb_write

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done

Comment on lines 1395 to 1397
/* from SDK because the zephyr CRC are no good for the bflb flash crc, this is supposedly a
* implementation of ZIP crc32
*/
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No good in what respect?

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It is a different algorithm / gives different results

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done

/* copy cfg reg to memory as cfg will not be in it and inaccessible */
data->reg_copy = cfg->reg;

/* get flash config using xip access */
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? Some leftover?

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No, it is designating all the code under it until the unlock

irq_unlock(locker);
return ret;
}
/* TODO: AES flash support goes here */
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Ever gonna do that TODO thing?

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It's for a future feature update

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done

Introduce Bouffalolab Flash Controller with support for bank 1

Signed-off-by: Camille BAUD <[email protected]>
Enable the Flash Controller

Signed-off-by: Camille BAUD <[email protected]>
Enable the flash controller. Relocation is required.

Signed-off-by: Camille BAUD <[email protected]>
Adds the flash to supported for testing

Signed-off-by: Camille BAUD <[email protected]>
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GREAT again hitting some global changes that aren't related to my PR!

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Please retry analysis of this Pull-Request directly on SonarQube Cloud

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4 participants