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dma: stm32: Clean up around usage of STM32_DMA_STREAM_OFFSET #94869

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Merged
merged 7 commits into from
Sep 3, 2025
Merged

dma: stm32: Clean up around usage of STM32_DMA_STREAM_OFFSET #94869

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67979f5
drivers: disk: sdmmc: stm32l4: Select DMA if enabled in dt
erwango Aug 21, 2025
068846c
drivers: dma: stm32u5: Clean up stream offset code
erwango Jul 25, 2025
bd9dcea
drivers: dma: stm32: Align channel offset handling in all API functions
erwango Aug 22, 2025
b191094
drivers: dma: stm32: Minor indentation fix
erwango Aug 22, 2025
6fb929c
drivers: stm32: Keep DMA stream offset handling internal to driver
erwango Aug 22, 2025
29633fd
include: drivers: stm32 dma: Provide a GET_INSTANCE macro
erwango Aug 22, 2025
d7e2581
drivers: stm32: Make use of new GET_INSTANCE DMA macro
erwango Aug 22, 2025
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2 changes: 1 addition & 1 deletion drivers/disk/Kconfig.sdmmc
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Original file line number Diff line number Diff line change
Expand Up @@ -38,7 +38,7 @@ config SDMMC_STM32
select USE_STM32_HAL_MMC_EX if SDMMC_STM32_EMMC && SOC_SERIES_STM32L4X
select USE_STM32_LL_SDMMC
select USE_STM32_HAL_DMA if (SOC_SERIES_STM32L4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32F4X)
select DMA if $(DT_STM32_SDMMC_HAS_DMA) && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X)
select DMA if $(DT_STM32_SDMMC_HAS_DMA) && (SOC_SERIES_STM32F4X || SOC_SERIES_STM32F7X || SOC_SERIES_STM32L4X)
select PINCTRL
select RESET
help
Expand Down
5 changes: 1 addition & 4 deletions drivers/disk/sdmmc_stm32.c
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Expand Up @@ -224,8 +224,8 @@ static int stm32_sdmmc_configure_dma(DMA_HandleTypeDef *handle, struct sdmmc_dma
return ret;
}

handle->Instance = STM32_DMA_GET_INSTANCE(dma->reg, dma->channel_nb);
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v1)
handle->Instance = __LL_DMA_GET_STREAM_INSTANCE(dma->reg, dma->channel_nb);
handle->Init.Channel = dma->cfg.dma_slot * DMA_CHANNEL_1;
handle->Init.PeriphInc = DMA_PINC_DISABLE;
handle->Init.MemInc = DMA_MINC_ENABLE;
Expand All @@ -238,14 +238,11 @@ static int stm32_sdmmc_configure_dma(DMA_HandleTypeDef *handle, struct sdmmc_dma
handle->Init.MemBurst = DMA_MBURST_INC4;
handle->Init.PeriphBurst = DMA_PBURST_INC4;
#else
uint32_t channel_id = dma->channel_nb - STM32_DMA_STREAM_OFFSET;

BUILD_ASSERT(STM32_SDMMC_USE_DMA_SHARED == 1, "Only txrx is supported on this family");
/* handle->Init.Direction is not initialised here on purpose.
* Since the channel is reused for both directions, the direction is
* configured before each read/write call.
*/
handle->Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dma->reg, channel_id);
handle->Init.Request = dma->cfg.dma_slot;
handle->Init.PeriphInc = DMA_PINC_DISABLE;
handle->Init.MemInc = DMA_MINC_ENABLE;
Expand Down
8 changes: 5 additions & 3 deletions drivers/dma/dma_stm32.c
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Original file line number Diff line number Diff line change
Expand Up @@ -273,10 +273,9 @@ DMA_STM32_EXPORT_API int dma_stm32_configure(const struct device *dev,
struct dma_config *config)
{
const struct dma_stm32_config *dev_config = dev->config;
struct dma_stm32_stream *stream =
&dev_config->streams[id - STM32_DMA_STREAM_OFFSET];
DMA_TypeDef *dma = (DMA_TypeDef *)dev_config->base;
LL_DMA_InitTypeDef DMA_InitStruct;
struct dma_stm32_stream *stream;
int ret;

LL_DMA_StructInit(&DMA_InitStruct);
Expand All @@ -289,6 +288,7 @@ DMA_STM32_EXPORT_API int dma_stm32_configure(const struct device *dev,
return -EINVAL;
}

stream = &dev_config->streams[id];
if (stream->busy) {
LOG_ERR("dma stream %d is busy.", id);
return -EBUSY;
Expand Down Expand Up @@ -594,8 +594,8 @@ DMA_STM32_EXPORT_API int dma_stm32_start(const struct device *dev, uint32_t id)
DMA_STM32_EXPORT_API int dma_stm32_stop(const struct device *dev, uint32_t id)
{
const struct dma_stm32_config *config = dev->config;
struct dma_stm32_stream *stream = &config->streams[id - STM32_DMA_STREAM_OFFSET];
DMA_TypeDef *dma = (DMA_TypeDef *)(config->base);
struct dma_stm32_stream *stream;

/* Give channel from index 0 */
id = id - STM32_DMA_STREAM_OFFSET;
Expand All @@ -604,6 +604,8 @@ DMA_STM32_EXPORT_API int dma_stm32_stop(const struct device *dev, uint32_t id)
return -EINVAL;
}

stream = &config->streams[id];

if (stream->hal_override) {
stream->busy = false;
return 0;
Expand Down
33 changes: 5 additions & 28 deletions drivers/dma/dma_stm32u5.c
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Expand Up @@ -265,9 +265,9 @@ static void dma_stm32_irq_handler(const struct device *dev, uint32_t id)
dma_stm32_clear_stream_irq(dev, id);
return;
}
callback_arg = id + STM32_DMA_STREAM_OFFSET;
callback_arg = id;

/* The dma stream id is in range from STM32_DMA_STREAM_OFFSET..<dma-requests> */
/* The dma stream id is in range from 0..<dma-requests> */
if (stm32_dma_is_ht_irq_active(dma, id)) {
/* Let HAL DMA handle flags on its own */
if (!stream->hal_override) {
Expand Down Expand Up @@ -349,16 +349,12 @@ static int dma_stm32_configure(const struct device *dev,
struct dma_config *config)
{
const struct dma_stm32_config *dev_config = dev->config;
struct dma_stm32_stream *stream =
&dev_config->streams[id - STM32_DMA_STREAM_OFFSET];
struct dma_stm32_stream *stream = &dev_config->streams[id];
DMA_TypeDef *dma = (DMA_TypeDef *)dev_config->base;
uint32_t ll_priority;
uint32_t ll_direction;
int ret;

/* Give channel from index 0 */
id = id - STM32_DMA_STREAM_OFFSET;

if (id >= dev_config->max_streams) {
LOG_ERR("cannot configure the dma stream %d.", id);
return -EINVAL;
Expand Down Expand Up @@ -553,9 +549,6 @@ static int dma_stm32_reload(const struct device *dev, uint32_t id,
DMA_TypeDef *dma = (DMA_TypeDef *)(config->base);
struct dma_stm32_stream *stream;

/* Give channel from index 0 */
id = id - STM32_DMA_STREAM_OFFSET;

if (id >= config->max_streams) {
return -EINVAL;
}
Expand All @@ -570,9 +563,7 @@ static int dma_stm32_reload(const struct device *dev, uint32_t id,
return -EINVAL;
}

LL_DMA_ConfigAddresses(dma,
dma_stm32_id_to_stream(id),
src, dst);
LL_DMA_ConfigAddresses(dma, dma_stm32_id_to_stream(id), src, dst);

LL_DMA_SetBlkDataLength(dma, dma_stm32_id_to_stream(id), size);

Expand All @@ -590,9 +581,6 @@ static int dma_stm32_start(const struct device *dev, uint32_t id)
DMA_TypeDef *dma = (DMA_TypeDef *)(config->base);
struct dma_stm32_stream *stream;

/* Give channel from index 0 */
id = id - STM32_DMA_STREAM_OFFSET;

/* Only M2P or M2M mode can be started manually. */
if (id >= config->max_streams) {
return -EINVAL;
Expand All @@ -619,9 +607,6 @@ static int dma_stm32_suspend(const struct device *dev, uint32_t id)
const struct dma_stm32_config *config = dev->config;
DMA_TypeDef *dma = (DMA_TypeDef *)(config->base);

/* Give channel from index 0 */
id = id - STM32_DMA_STREAM_OFFSET;

if (id >= config->max_streams) {
return -EINVAL;
}
Expand All @@ -642,9 +627,6 @@ static int dma_stm32_resume(const struct device *dev, uint32_t id)
const struct dma_stm32_config *config = dev->config;
DMA_TypeDef *dma = (DMA_TypeDef *)(config->base);

/* Give channel from index 0 */
id = id - STM32_DMA_STREAM_OFFSET;

if (id >= config->max_streams) {
return -EINVAL;
}
Expand All @@ -658,12 +640,9 @@ static int dma_stm32_resume(const struct device *dev, uint32_t id)
static int dma_stm32_stop(const struct device *dev, uint32_t id)
{
const struct dma_stm32_config *config = dev->config;
struct dma_stm32_stream *stream = &config->streams[id - STM32_DMA_STREAM_OFFSET];
struct dma_stm32_stream *stream = &config->streams[id];
DMA_TypeDef *dma = (DMA_TypeDef *)(config->base);

/* Give channel from index 0 */
id = id - STM32_DMA_STREAM_OFFSET;

if (id >= config->max_streams) {
return -EINVAL;
}
Expand Down Expand Up @@ -723,8 +702,6 @@ static int dma_stm32_get_status(const struct device *dev,
DMA_TypeDef *dma = (DMA_TypeDef *)(config->base);
struct dma_stm32_stream *stream;

/* Give channel from index 0 */
id = id - STM32_DMA_STREAM_OFFSET;
if (id >= config->max_streams) {
return -EINVAL;
}
Expand Down
24 changes: 3 additions & 21 deletions drivers/flash/flash_stm32_ospi.c
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Expand Up @@ -2219,12 +2219,9 @@ static int flash_stm32_ospi_init(const struct device *dev)
dma_cfg.user_data = &hdma;
/* HACK: This field is used to inform driver that it is overridden */
dma_cfg.linked_channel = STM32_DMA_HAL_OVERRIDE;
/* Because of the STREAM OFFSET, the DMA channel given here is from 1 - 8 */
ret = dma_config(dev_data->dma.dev,
(dev_data->dma.channel + STM32_DMA_STREAM_OFFSET), &dma_cfg);
ret = dma_config(dev_data->dma.dev, dev_data->dma.channel, &dma_cfg);
if (ret != 0) {
LOG_ERR("Failed to configure DMA channel %d",
dev_data->dma.channel + STM32_DMA_STREAM_OFFSET);
LOG_ERR("Failed to configure DMA channel %d", dev_data->dma.channel);
return ret;
}

Expand Down Expand Up @@ -2256,27 +2253,12 @@ static int flash_stm32_ospi_init(const struct device *dev)
hdma.Init.Mode = DMA_NORMAL;
hdma.Init.Priority = table_priority[dma_cfg.channel_priority];
hdma.Init.Direction = DMA_PERIPH_TO_MEMORY;
hdma.Instance = STM32_DMA_GET_INSTANCE(dev_data->dma.reg, dev_data->dma.channel);
#ifdef CONFIG_DMA_STM32_V1
/* TODO: Not tested in this configuration */
hdma.Init.Channel = dma_cfg.dma_slot;
hdma.Instance = __LL_DMA_GET_STREAM_INSTANCE(dev_data->dma.reg,
dev_data->dma.channel);
#else
hdma.Init.Request = dma_cfg.dma_slot;
#if CONFIG_DMA_STM32U5
hdma.Instance = LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg,
dev_data->dma.channel);
#elif defined(CONFIG_DMAMUX_STM32)
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Is CONFIG_DMAMUX_STM32=y properly considered in the new STM32_DMA_GET_INSTANCE() macro?

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Actually, this macro only abstract LL_DMA_GET_CHANNEL_INSTANCE vs __LL_DMA_GET_STREAM_INSTANCE which doesn't depend on CONFIG_DMAMUX_STM32. Then the offset consideration, which can be impacted by CONFIG_DMAMUX_STM32 is taken care by systematic use of STM32_DMA_STREAM_OFFSET.

/*
* HAL expects a valid DMA channel (not DMAMUX).
* The channel is from 0 to 7 because of the STM32_DMA_STREAM_OFFSET in the dma_stm32 driver
*/
hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg,
dev_data->dma.channel);
#else
hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg,
dev_data->dma.channel-1);
#endif /* CONFIG_DMA_STM32U5 */
#endif /* CONFIG_DMA_STM32_V1 */

/* Initialize DMA HAL */
Expand Down
11 changes: 1 addition & 10 deletions drivers/flash/flash_stm32_qspi.c
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Expand Up @@ -1592,21 +1592,12 @@ static int flash_stm32_qspi_init(const struct device *dev)
hdma.Init.MemInc = DMA_MINC_ENABLE;
hdma.Init.Mode = DMA_NORMAL;
hdma.Init.Priority = table_priority[dma_cfg.channel_priority];
hdma.Instance = STM32_DMA_GET_INSTANCE(dev_data->dma.reg, dev_data->dma.channel);
#ifdef CONFIG_DMA_STM32_V1
/* TODO: Not tested in this configuration */
hdma.Init.Channel = dma_cfg.dma_slot;
hdma.Instance = __LL_DMA_GET_STREAM_INSTANCE(dev_data->dma.reg,
dev_data->dma.channel);
#else
hdma.Init.Request = dma_cfg.dma_slot;
#ifdef CONFIG_DMAMUX_STM32
/* HAL expects a valid DMA channel (not a DMAMUX channel) */
hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg,
dev_data->dma.channel);
#else
hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(dev_data->dma.reg,
dev_data->dma.channel-1);
#endif
#endif /* CONFIG_DMA_STM32_V1 */

/* Initialize DMA HAL */
Expand Down
7 changes: 2 additions & 5 deletions drivers/flash/flash_stm32_xspi.c
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Expand Up @@ -1977,12 +1977,9 @@ static int flash_stm32_xspi_dma_init(DMA_HandleTypeDef *hdma, struct stream *dma
dma_stream->cfg.user_data = hdma;
/* HACK: This field is used to inform driver that it is overridden */
dma_stream->cfg.linked_channel = STM32_DMA_HAL_OVERRIDE;
/* Because of the STREAM OFFSET, the DMA channel given here is from 1 - 8 */
ret = dma_config(dma_stream->dev,
(dma_stream->channel + STM32_DMA_STREAM_OFFSET), &dma_stream->cfg);
ret = dma_config(dma_stream->dev, dma_stream->channel, &dma_stream->cfg);
if (ret != 0) {
LOG_ERR("Failed to configure DMA channel %d",
dma_stream->channel + STM32_DMA_STREAM_OFFSET);
LOG_ERR("Failed to configure DMA channel %d", dma_stream->channel);
return ret;
}

Expand Down
12 changes: 3 additions & 9 deletions drivers/i2s/i2s_stm32_sai.c
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Expand Up @@ -17,8 +17,6 @@
#include <zephyr/drivers/pinctrl.h>
#include <zephyr/cache.h>

#include <zephyr/drivers/dma/dma_stm32.h>
#include <zephyr/drivers/dma.h>
#include <stm32_ll_dma.h>

#include <zephyr/logging/log.h>
Expand Down Expand Up @@ -276,23 +274,19 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
/* HACK: This field is used to inform driver that it is overridden */
dma_cfg.linked_channel = STM32_DMA_HAL_OVERRIDE;

/* Because of the STREAM OFFSET, the DMA channel given here is from 1 - 8 */
ret = dma_config(stream->dma_dev, stream->dma_channel + STM32_DMA_STREAM_OFFSET, &dma_cfg);
ret = dma_config(stream->dma_dev, stream->dma_channel, &dma_cfg);

if (ret != 0) {
LOG_ERR("Failed to configure DMA channel %d",
stream->dma_channel + STM32_DMA_STREAM_OFFSET);
LOG_ERR("Failed to configure DMA channel %d", stream->dma_channel);
return ret;
}

#if defined(CONFIG_SOC_SERIES_STM32H7X)
hdma->Instance = __LL_DMA_GET_STREAM_INSTANCE(stream->reg, stream->dma_channel);
hdma->Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
hdma->Init.MemDataAlignment = DMA_PDATAALIGN_HALFWORD;
hdma->Init.Priority = DMA_PRIORITY_HIGH;
hdma->Init.FIFOMode = DMA_FIFOMODE_DISABLE;
#else
hdma->Instance = LL_DMA_GET_CHANNEL_INSTANCE(stream->reg, stream->dma_channel);
hdma->Init.BlkHWRequest = DMA_BREQ_SINGLE_BURST;
hdma->Init.SrcDataWidth = DMA_SRC_DATAWIDTH_HALFWORD;
hdma->Init.DestDataWidth = DMA_DEST_DATAWIDTH_HALFWORD;
Expand All @@ -302,7 +296,7 @@ static int i2s_stm32_sai_dma_init(const struct device *dev)
hdma->Init.TransferAllocatedPort = DMA_SRC_ALLOCATED_PORT0 | DMA_DEST_ALLOCATED_PORT0;
hdma->Init.TransferEventMode = DMA_TCEM_BLOCK_TRANSFER;
#endif

hdma->Instance = STM32_DMA_GET_INSTANCE(stream->reg, stream->dma_channel);
hdma->Init.Request = dma_cfg.dma_slot;
hdma->Init.Mode = DMA_NORMAL;

Expand Down
16 changes: 4 additions & 12 deletions drivers/video/video_stm32_dcmi.c
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Expand Up @@ -136,12 +136,9 @@ static int stm32_dma_init(const struct device *dev)
dma_cfg.user_data = &hdma;
/* HACK: This field is used to inform driver that it is overridden */
dma_cfg.linked_channel = STM32_DMA_HAL_OVERRIDE;
/* Because of the STREAM OFFSET, the DMA channel given here is from 1 - 8 */
ret = dma_config(config->dma.dma_dev,
config->dma.channel + STM32_DMA_STREAM_OFFSET, &dma_cfg);
ret = dma_config(config->dma.dma_dev, config->dma.channel, &dma_cfg);
if (ret != 0) {
LOG_ERR("Failed to configure DMA channel %d",
config->dma.channel + STM32_DMA_STREAM_OFFSET);
LOG_ERR("Failed to configure DMA channel %d", config->dma.channel);
return ret;
}

Expand All @@ -155,17 +152,12 @@ static int stm32_dma_init(const struct device *dev)
hdma.Init.MemDataAlignment = DMA_MDATAALIGN_WORD;
hdma.Init.Mode = DMA_CIRCULAR;
hdma.Init.Priority = DMA_PRIORITY_HIGH;
hdma.Instance = STM32_DMA_GET_INSTANCE(config->dma.reg,
config->dma.channel);
#if defined(CONFIG_SOC_SERIES_STM32F7X) || defined(CONFIG_SOC_SERIES_STM32H7X)
hdma.Init.FIFOMode = DMA_FIFOMODE_DISABLE;
#endif

#if defined(CONFIG_SOC_SERIES_STM32F7X) || defined(CONFIG_SOC_SERIES_STM32H7X)
hdma.Instance = __LL_DMA_GET_STREAM_INSTANCE(config->dma.reg,
config->dma.channel);
#elif defined(CONFIG_SOC_SERIES_STM32L4X)
hdma.Instance = __LL_DMA_GET_CHANNEL_INSTANCE(config->dma.reg, config->dma.channel);
#endif

/* Initialize DMA HAL */
__HAL_LINKDMA(&data->hdcmi, DMA_Handle, hdma);

Expand Down
8 changes: 8 additions & 0 deletions include/zephyr/drivers/dma/dma_stm32.h
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Expand Up @@ -85,4 +85,12 @@
#define STM32_DMA_FEATURES_FIFO_THRESHOLD(features) 0
#endif

#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32_dma_v1)
#define STM32_DMA_GET_INSTANCE(reg, channel) \
__LL_DMA_GET_STREAM_INSTANCE((reg), (channel) - STM32_DMA_STREAM_OFFSET);
#else
#define STM32_DMA_GET_INSTANCE(reg, channel) \
__LL_DMA_GET_CHANNEL_INSTANCE((reg), (channel) - STM32_DMA_STREAM_OFFSET);
#endif

#endif /* ZEPHYR_INCLUDE_DRIVERS_DMA_STM32_H_ */
1 change: 0 additions & 1 deletion tests/drivers/disk/disk_access/boards/stm32l496g_disco_stm32l496xx.conf
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