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drivers: crypto: hash driver for the STM32H7RS series #94749

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drivers: crypto: hash driver for the STM32H7RS series #94749

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976343a
drivers: crypto: hash driver supports the stm32h7rs series
FRASTM Aug 20, 2025
8ee2c29
dts: arm: stm32h7RS devices have HASH node
FRASTM Aug 20, 2025
35abe4e
boards: st: nucleo_h7s3l8 board enables HASH node
FRASTM Aug 20, 2025
d6cb04f
tests: crypto: Add stm32h7rs target boards support to crypto_hash test
FRASTM Aug 20, 2025
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4 changes: 4 additions & 0 deletions boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -144,6 +144,10 @@
status = "okay";
};

&hash {
status = "okay";
};

&adc1 {
pinctrl-0 = <&adc1_inp15_pa3>; /* Arduino A0 */
pinctrl-names = "default";
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18 changes: 13 additions & 5 deletions drivers/crypto/crypto_stm32_hash.c
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Expand Up @@ -62,12 +62,14 @@ static int stm32_hash_handler(struct hash_ctx *ctx, struct hash_pkt *pkt, bool f

switch (session->algo) {
case CRYPTO_HASH_ALGO_SHA224:
status = HAL_HASHEx_SHA224_Start(&data->hhash, pkt->in_buf, pkt->in_len,
pkt->out_buf, HAL_MAX_DELAY);
LOG_DBG("HASH compute SHA224");
status = hal_func_hash_SHA224_start(&data->hhash, pkt->in_buf, pkt->in_len,
pkt->out_buf);
break;
case CRYPTO_HASH_ALGO_SHA256:
status = HAL_HASHEx_SHA256_Start(&data->hhash, pkt->in_buf, pkt->in_len,
pkt->out_buf, HAL_MAX_DELAY);
LOG_DBG("HASH compute SHA256");
status = hal_func_hash_SHA256_start(&data->hhash, pkt->in_buf, pkt->in_len,
pkt->out_buf);
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Indentation

		status = hal_func_hash_SHA256_start(&data->hhash, pkt->in_buf, pkt->in_len,
						    pkt->out_buf);

break;
default:
k_sem_give(&data->device_sem);
Expand Down Expand Up @@ -175,7 +177,13 @@ static DEVICE_API(crypto, stm32_hash_funcs) = {
.query_hw_caps = stm32_hash_query_caps,
};

static struct crypto_stm32_hash_data crypto_stm32_hash_dev_data = {0};
static struct crypto_stm32_hash_data crypto_stm32_hash_dev_data = {
#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
.hhash = {.Instance = (HASH_TypeDef *)DT_INST_REG_ADDR(0)}
#else
0
#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
};

static const struct crypto_stm32_hash_config crypto_stm32_hash_dev_config = {
.reset = RESET_DT_SPEC_INST_GET(0),
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48 changes: 46 additions & 2 deletions drivers/crypto/crypto_stm32_hash_priv.h
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Expand Up @@ -7,11 +7,24 @@
#ifndef ZEPHYR_DRIVERS_CRYPTO_CRYPTO_STM32_HASH_PRIV_H_
#define ZEPHYR_DRIVERS_CRYPTO_CRYPTO_STM32_HASH_PRIV_H_

#define hash_config_t HASH_InitTypeDef

/* Max digest length: SHA256 = 32 bytes */
#define STM32_HASH_MAX_DIGEST_SIZE (32)

#if defined(CONFIG_SOC_SERIES_STM32H7RSX)

#define hash_config_t HASH_ConfigTypeDef
#define HASH_DATATYPE_8B HASH_BYTE_SWAP
#define STM32_HASH_SHA224_START HAL_HASH_Start
#define STM32_HASH_SHA256_START HAL_HASH_Start

#else /* CONFIG_SOC_SERIES_STM32H7RSX */

#define hash_config_t HASH_InitTypeDef
#define STM32_HASH_SHA224_START HAL_HASHEx_SHA224_Start
#define STM32_HASH_SHA256_START HAL_HASHEx_SHA256_Start

#endif /* CONFIG_SOC_SERIES_STM32H7RSX */

struct crypto_stm32_hash_config {
const struct reset_dt_spec reset;
struct stm32_pclken pclken;
Expand All @@ -37,4 +50,35 @@ struct crypto_stm32_hash_session {
#define CRYPTO_STM32_HASH_SESSN(ctx) \
((struct crypto_stm32_hash_session *const)(ctx)->drv_sessn_state)

static inline HAL_StatusTypeDef hal_func_hash_SHA224_start(HASH_HandleTypeDef *hhash,
void *p_in_buffer,
uint32_t in_size_byte,
void *p_out_buffer)
Comment on lines +53 to +56
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Indenattion

static inline HAL_StatusTypeDef hal_func_hash_SHA224_start(HASH_HandleTypeDef *hhash,
							   void *p_in_buffer,
							   uint32_t in_size_byte,
							   void *p_out_buffer)

Ditto for hal_func_hash_SHA256_start().

{
#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
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From what I can see, this implementation (calling HAL_HASH_SetConfig()/HAL_HASH_Start() instead of HAL_HASHEx_SHA224_Start() is also common with other all recent STM32 series (H5,MP2,N6,U3,WBA).

In order to avoid updating driver code with || defined(CONFIG_SOC_SERIES_STM32FOO) for each new series, let's define a new Kconfig (CRYPTO_STM32_HASH_HAL_CFG_START for instance) that would be selected by these series when driver support is added. That would minimize effort to add new series and be better for code readability.
(I'm not proposing a new compatible, as I think this is not an issue of HW, but pure HAL implementation, but I could be wrong)

hhash->Init.Algorithm = HASH_ALGOSELECTION_SHA224;
if (HAL_HASH_SetConfig(hhash, &hhash->Init) != HAL_OK) {
return HAL_ERROR;
}
#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
return STM32_HASH_SHA224_START(hhash, p_in_buffer, in_size_byte, p_out_buffer,
HAL_MAX_DELAY);
}

static inline HAL_StatusTypeDef hal_func_hash_SHA256_start(HASH_HandleTypeDef *hhash,
void *p_in_buffer,
uint32_t in_size_byte,
void *p_out_buffer)
{
#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
hhash->Init.Algorithm = HASH_ALGOSELECTION_SHA256;

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nitpicking consistency: remove this empty line, as in hal_func_hash_SHA224_start().

if (HAL_HASH_SetConfig(hhash, &hhash->Init) != HAL_OK) {
return HAL_ERROR;
}
#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
return STM32_HASH_SHA256_START(hhash, p_in_buffer, in_size_byte, p_out_buffer,
HAL_MAX_DELAY);
}

#endif /* ZEPHYR_DRIVERS_CRYPTO_CRYPTO_STM32_HASH_PRIV_H_ */
9 changes: 9 additions & 0 deletions dts/arm/st/h7rs/stm32h7rs.dtsi
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Expand Up @@ -534,6 +534,15 @@
status = "disabled";
};

hash: hash@48020400 {
compatible = "st,stm32-hash";
reg = <0x48020400 0x400>;
clocks = <&rcc STM32_CLOCK(AHB3, 1)>;
resets = <&rctl STM32_RESET(AHB3, 1)>;
interrupts = <36 0>;
status = "disabled";
};

timers1: timers@42000000 {
compatible = "st,stm32-timers";
reg = <0x42000000 0x400>;
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1 change: 1 addition & 0 deletions tests/crypto/crypto_hash/testcase.yaml
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Expand Up @@ -2,6 +2,7 @@ tests:
crypto.hash:
platform_allow:
- native_sim
- nucleo_h7s3l8
- nucleo_u575zi_q
integration_platforms:
- native_sim
Expand Down