Add STM32MP13 support

arch/arm/core/cortex_a_r/Kconfig

@@ -13,6 +13,15 @@
 # CPU_AARCH32_CORTEX_A / if CPU_AARCH32_CORTEX_R blocks so they are not
 # exposed if one selects a different ARM Cortex Family (Cortex-M).
 
+config CPU_CORTEX_A7
+	bool
+	select CPU_AARCH32_CORTEX_A
+	select ARMV7_A
+	select CPU_HAS_ICACHE
+	select CPU_HAS_DCACHE
+	help
+	  This option signifies the use of a Cortex-A7 CPU.
+
 config CPU_CORTEX_A9
 	bool
 	select CPU_AARCH32_CORTEX_A

arch/arm/core/cortex_a_r/fault.c

@@ -100,6 +100,59 @@ static uint32_t dump_fault(uint32_t status, uint32_t addr)
 		reason = K_ERR_ARM_UNSUPPORTED_EXCLUSIVE_ACCESS_FAULT;
 		LOG_ERR("Unsupported Exclusive Access Fault @ 0x%08x", addr);
 		break;
+#elif defined(CONFIG_ARMV7_A)
+	case FSR_FS_PERMISSION_FAULT_2ND_LEVEL:
+		reason = K_ERR_ARM_PERMISSION_FAULT_2ND_LEVEL;
+		LOG_ERR("2nd Level Permission Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_ACCESS_FLAG_FAULT_1ST_LEVEL:
+		reason = K_ERR_ARM_ACCESS_FLAG_FAULT_1ST_LEVEL;
+		LOG_ERR("1st Level Access Flag Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_ACCESS_FLAG_FAULT_2ND_LEVEL:
+		reason = K_ERR_ARM_ACCESS_FLAG_FAULT_2ND_LEVEL;
+		LOG_ERR("2nd Level Access Flag Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_CACHE_MAINTENANCE_INSTRUCTION_FAULT:
+		reason = K_ERR_ARM_CACHE_MAINTENANCE_INSTRUCTION_FAULT;
+		LOG_ERR("Cache Maintenance Instruction Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_TRANSLATION_FAULT:
+		reason = K_ERR_ARM_TRANSLATION_FAULT;
+		LOG_ERR("1st Level Translation Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_TRANSLATION_FAULT_2ND_LEVEL:
+		reason = K_ERR_ARM_TRANSLATION_FAULT_2ND_LEVEL;
+		LOG_ERR("2nd Level Translation Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_DOMAIN_FAULT_1ST_LEVEL:
+		reason = K_ERR_ARM_DOMAIN_FAULT_1ST_LEVEL;
+		LOG_ERR("1st Level Domain Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_DOMAIN_FAULT_2ND_LEVEL:
+		reason = K_ERR_ARM_DOMAIN_FAULT_2ND_LEVEL;
+		LOG_ERR("2nd Level Domain Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_1ST_LEVEL:
+		reason = K_ERR_ARM_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_1ST_LEVEL;
+		LOG_ERR("1st Level Synchronous External Abort Translation Table @ 0x%08x", addr);
+		break;
+	case FSR_FS_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_2ND_LEVEL:
+		reason = K_ERR_ARM_SYNC_EXTERNAL_ABORT_TRANSLATION_TABLE_2ND_LEVEL;
+		LOG_ERR("2nd Level Synchronous External Abort Translation Table @ 0x%08x", addr);
+		break;
+	case FSR_FS_TLB_CONFLICT_FAULT:
+		reason = K_ERR_ARM_TLB_CONFLICT_FAULT;
+		LOG_ERR("Table Conflict Fault @ 0x%08x", addr);
+		break;
+	case FSR_FS_SYNC_PARITY_ERROR_TRANSLATION_TABLE_1ST_LEVEL:
+		reason = K_ERR_ARM_SYNC_PARITY_ERROR_TRANSLATION_TABLE_1ST_LEVEL;
+		LOG_ERR("1st Level Synchronous Parity Error Translation Table @ 0x%08x", addr);
+		break;
+	case FSR_FS_SYNC_PARITY_ERROR_TRANSLATION_TABLE_2ND_LEVEL:
+		reason = K_ERR_ARM_SYNC_PARITY_ERROR_TRANSLATION_TABLE_2ND_LEVEL;
+		LOG_ERR("2nd Level Synchronous Parity Error Translation Table @ 0x%08x", addr);
+		break;
 #else
 	case FSR_FS_BACKGROUND_FAULT:
 		reason = K_ERR_ARM_BACKGROUND_FAULT;

boards/st/stm32mp135f_dk/Kconfig.stm32mp135f_dk

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_STM32MP135F_DK
+	select SOC_STM32MP135FXX

boards/st/stm32mp135f_dk/board.cmake

@@ -0,0 +1,6 @@
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)
+
+board_runner_args(openocd "--config=${BOARD_DIR}/support/openocd.cfg")

boards/st/stm32mp135f_dk/board.yml

@@ -0,0 +1,6 @@
+board:
+  name: stm32mp135f_dk
+  full_name: STM32MP135F-DK Discovery
+  vendor: st
+  socs:
+    - name: stm32mp135fxx

boards/st/stm32mp135f_dk/doc/index.rst

@@ -0,0 +1,203 @@
+.. zephyr:board:: stm32mp135f_dk
+
+Overview
+********
+The STM32MP135 Discovery kit (STM32MP135F-DK) leverages the capabilities of the
+1 GHz STM32MP135 microprocessors to allow users to develop applications easily with Zephyr RTOS.
+
+It includes an ST-LINK embedded debug tool, LEDs, push-buttons, two 10/100 Mbit/s Ethernet (RMII) connectors, one USB Type-C |reg| connector, four USB Host Type-A connectors, and one microSD™ connector.
+
+To expand the functionality of the STM32MP135 Discovery kit, one GPIO expansion connector is also available for third-party shields.
+
+Additionally, the STM32MP135 Discovery kit features an LCD display with a touch panel, Wi‑Fi |reg| and Bluetooth |reg| Low Energy capability, and a 2-megapixel CMOS camera module.
+
+It also provides secure boot and cryptography features.
+
+Zephyr OS is ported to run on the Cortex |reg|-A7 core.
+
+- STM32MP135FAF7: Arm |reg| Cortex |reg|-A7 32-bit processor at 1 GHz, in a TFBGA320 package
+- ST PMIC STPMIC1
+- 4-Gbit DDR3L, 16 bits, 533 MHz
+- 4.3" 480x272 pixels LCD display module with capacitive touch panel and RGB interface
+- UXGA 2-megapixel CMOS camera module (included) with MIPI CSI-2 |reg| / SMIA CCP2 deserializer
+- Wi-Fi |reg| 802.11b/g/n
+- Bluetooth |reg| Low Energy 4.1
+- Dual 10/100 Mbit/s Ethernet (RMII) compliant with IEEE-802.3u, one with Wake on LAN (WoL) support
+- USB Host 4-port hub
+- USB Type-C |reg| DRP based on an STM32G0 device
+- 4 user LEDs
+- 4 push-buttons (2× user, tamper, and reset)
+- 1 wake-up button
+- Board connectors:
+
+  - Dual-lane MIPI CSI-2 |reg| camera module expansion
+  - 2x Ethernet RJ45
+  - 4x USB Type-A
+  - USB Micro-B
+  - USB Type-C |reg|
+  - microSD™ card holder
+  - GPIO expansion
+  - 5 V / 3 A USB Type-C |reg| power supply input (charger not provided)
+  - VBAT for power backup
+
+- On-board current measurement
+- On-board STLINK-V3E debugger/programmer with USB re-enumeration capability:
+
+  - mass storage
+  - Virtual COM port
+  - debug port
+
+More information about the board can be found at the
+`STM32P135 Discovery website`_.
+
+Hardware
+********
+
+More information about the STM32MP135F_DK board hardware can be found here:
+
+- `STM32MP135F_DK Hardware Description`_
+
+More information about STM32P135F microprocessor can be found here:
+
+- `STM32MP135F on www.st.com`_
+- `STM32MP135F reference manual`_
+
+Supported Features
+==================
+
+.. zephyr:board-supported-hw::
+
+Connections and IOs
+===================
+
+STM32MP135F-DK Discovery Board schematic is available here:
+`STM32MP135F Discovery board schematics`_.
+
+
+Default Zephyr Peripheral Mapping:
+----------------------------------
+
+- USART_4 TX/RX : PD6/PD8 (UART console)
+
+- USER_BUTTON : PA13
+- LED_3 : PA14
+- LED_4 : PA13
+
+System Clock
+------------
+
+The Cortex |reg|-A7 core is configured to run at a clock speed of up to 1GHz.
+
+Memory mapping
+--------------
+
++------------+-----------------------+----------------+
+| Region     |        Address        |     Size       |
++============+=======================+================+
+| SYSRAM     | 0x2FFE0000-0x2FFFFFFF | 128KB          |
++------------+-----------------------+----------------+
+| SRAM 1     | 0x30000000-0x30003FFF |  16KB          |
++------------+-----------------------+----------------+
+| SRAM 2     | 0x30004000-0x30005FFF |   8KB          |
++------------+-----------------------+----------------+
+| SRAM 3     | 0x30006000-0x30007FFF |   8KB          |
++------------+-----------------------+----------------+
+| DDR        | 0xC0000000-0xDFFFFFFF |   512 MB       |
++------------+-----------------------+----------------+
+
+Programming and Debugging
+*************************
+
+Prerequisite
+============
+
+The STM32MP135 has a DDR controller that need to be initialized before loading the Zephyr example.
+
+One method to perform this is to flash the Zephyr executable, along with the DDR initialization script, on an SD card inserted in the board. To do so, you first need to :ref:`install STM32CubeProgrammer <stm32cubeprog-flash-host-tools>` and download the `STM32CubeMP13 package`_.
+
+Signature and flashing
+======================
+
+After building the Zephyr project, you need to sign your binary file using the Stm32ImageAddHeader.py with the following command:
+
+.. code-block:: console
+
+   python3 ${Path_to_STM32CubeMP13}/Utilities/ImageHeader/Python3/Stm32ImageAddHeader.py ${Path_to_build_dir}/zephyr/zephyr.bin ${STM32CubeMP13}/Projects/STM32MP135C-DK/External_Loader/Prebuild_Binaries/SD_Ext_Loader/zephyr_Signed.bin -bt 10 -la C0000000 -ep C0000000
+
+Here -bt specifies the boot type, -la specifies the load address and -ep the entry point for your executable (same as the load address in this case).
+
+Then, copy :zephyr_file:`boards/st/stm32mp135f_dk/support/Zephyr.tsv` to ``${Path_to_STM32CubeMP13}/Projects/STM32MP135C-DK/External_Loader/Prebuild_Binaries/SD_Ext_Loader/``.
+
+Finally using the Cube Programmer select the Zephyr.tsv and flash the SD card with the following command:
+
+.. code-block:: console
+
+   ${Path_to_STM32cube_Programmer}/bin/STM32_Programmer.sh -c port=${ConnectedPort} p=even br=115200 -d ${Path_to_STM32CubeMP13}/Projects/STM32MP135C-DK/External_Loader/Prebuild_Binaries/SD_Ext_Loader/Zephyr.tsv
+
+.. note::
+  You can refer to this example to flash an example to the SD card:
+  `How to install STM32Cube software package on microSD card`_
+
+Debugging
+=========
+
+You can debug an application using OpenOCD and GDB.
+
+- Build the sample:
+
+  .. zephyr-app-commands::
+     :zephyr-app: samples/hello_world
+     :board: stm32mp135f_dk
+     :goals: build
+
+- Flash the SD card using:
+  `How to install STM32Cube software package on microSD card`_
+
+- Run the application from the SD card
+
+- Attach to the target:
+
+  .. code-block:: console
+
+      west attach
+
+.. note::
+  The ``run`` command of GDB isn't supported at the moment for this board.
+
+References
+**********
+
+.. target-notes::
+
+.. _STM32P135 Discovery website:
+   https://www.st.com/en/evaluation-tools/stm32mp135f-dk.html
+
+.. _STM32MP135F Discovery board User Manual:
+   https://www.st.com/resource/en/user_manual/dm00862450.pdf
+
+.. _STM32MP135F Discovery board schematics:
+   https://www.st.com/resource/en/schematic_pack/mb1635-mp135f-e02-schematic.pdf
+
+.. _STM32MP135F on www.st.com:
+   https://www.st.com/content/st_com/en/products/microcontrollers-microprocessors/stm32-arm-cortex-mpus/stm32mp1-series/stm32mp135/stm32mp135f.html
+
+.. _STM32MP135F reference manual:
+   https://www.st.com/resource/en/reference_manual/DM00670465-.pdf
+
+.. _STM32MP135 STM32Cube software package:
+   https://www.st.com/en/embedded-software/stm32cubemp13.html#get-software
+
+.. _How to install STM32Cube software package on microSD card:
+   https://wiki.st.com/stm32mpu/wiki/How_to_load_and_start_STM32CubeMP13_applications_via_microSD_card
+
+.. _STM32MP135F boot architecture:
+   https://wiki.st.com/stm32mpu/wiki/STM32CubeMP13_package_-_boot_architecture
+
+.. _STM32MP135F baremetal distribution:
+   https://wiki.st.com/stm32mpu/wiki/Category:Bare_metal_-_RTOS_embedded_software
+
+.. _STM32CubeMP13 package:
+   https://github.com/STMicroelectronics/STM32CubeMP13
+
+.. _STM32MP135F_DK Hardware Description:
+   https://wiki.stmicroelectronics.cn/stm32mpu/wiki/STM32MP135x-DK_-_hardware_description

boards/st/stm32mp135f_dk/stm32mp135f_dk.dts

@@ -0,0 +1,93 @@
+/*
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <st/mp13/stm32mp135.dtsi>
+#include <st/mp13/stm32mp135faex-pinctrl.dtsi>
+#include <zephyr/dt-bindings/input/input-event-codes.h>
+
+/ {
+	model = "STMicroelectronics STM32MP135-DK board";
+	compatible = "st,stm32mp135f-dk";
+
+	chosen {
+		zephyr,flash = &ddr_code;
+		zephyr,sram = &ddr_data;
+		zephyr,console = &uart4;
+		zephyr,shell-uart = &uart4;
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+
+		user_button: button {
+			label = "User 1";
+			gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
+			zephyr,code = <INPUT_KEY_0>;
+		};
+	};
+
+	leds {
+		compatible = "gpio-leds";
+
+		blue_led_1: led_1 {
+			gpios = <&gpioa 14 GPIO_ACTIVE_HIGH>;
+			label = "LD3";
+		};
+
+		red_led_2: led_2 {
+			gpios = <&gpioa 13 GPIO_ACTIVE_HIGH>;
+			label = "LD4";
+		};
+	};
+
+	aliases {
+		led0 = &blue_led_1;
+		led1 = &red_led_2;
+		sw0 = &user_button;
+	};
+};
+
+&clk_hsi {
+	clock-frequency = <DT_FREQ_M(64)>;
+	status = "okay";
+};
+
+&clk_hse {
+	clock-frequency = <DT_FREQ_M(24)>;
+	status = "okay";
+};
+
+&cpusw {
+	clocks = <&clk_hsi>;
+	clock-frequency = <DT_FREQ_M(64)>;
+	status = "okay";
+};
+
+&pll1 {
+	clocks = <&clk_hse>;
+	div-m = <2>;
+	mul-n = <83>;
+	div-p = <1>;
+	frac-v = <2730>;
+	status = "okay";
+};
+
+&rcc {
+	clock-frequency = <DT_FREQ_M(1000)>;
+	clocks = <&pll>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+};
+
+&uart4 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&uart4_tx_pd6 &uart4_rx_pd8>;
+	current-speed = <115200>;
+	status = "okay";
+};