Post 4.1 merge fix h7 usb

boards/arduino/giga_r1/arduino_giga_r1_stm32h747xx_m7.dts

@@ -252,3 +252,9 @@ zephyr_udc0: &usbotg_fs {
 	pinctrl-0 = <&usb_otg_fs_dm_pa11 &usb_otg_fs_dp_pa12>;
 	pinctrl-names = "default";
 };
+
+/* alias used by display shields */
+zephyr_mipi_dsi: &mipi_dsi {};
+
+/* alias used by LCD display shields */
+zephyr_lcd_controller: &ltdc {};

boards/arduino/portenta_c33/CMakeLists.txt

@@ -0,0 +1,4 @@
+# Copyright 2025 Arduino SA
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_sources_ifdef(CONFIG_NETWORKING eth_pwm_clock.c)

boards/arduino/portenta_c33/Kconfig.arduino_portenta_c33

@@ -0,0 +1,5 @@
+# Copyright (c) 2025 Arduino SA
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_ARDUINO_PORTENTA_C33
+	select SOC_R7FA6M5BH3CFC

boards/arduino/portenta_c33/Kconfig.defconfig

@@ -0,0 +1,13 @@
+# Copyright 2024 Rahul Arasikere <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_ARDUINO_PORTENTA_C33
+
+if NETWORKING
+
+config NET_L2_ETHERNET
+	default y
+
+endif # NETWORKING
+
+endif # BOARD_ARDUINO_PORTENTA_C33

boards/arduino/portenta_c33/arduino_portenta_c33-pinctrl.dtsi

@@ -0,0 +1,152 @@
+/*
+ * Copyright (c) 2024 Arduino SA
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+&pinctrl {
+	sci7_default: sci7_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_7, 6, 13)>,
+				<RA_PSEL(RA_PSEL_SCI_7, 6, 14)>,
+				<RA_PSEL(RA_PSEL_SCI_7, 6, 11)>,
+				<RA_PSEL(RA_PSEL_SCI_7, 4, 4)>;
+		};
+	};
+
+	sci9_default: sci9_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_9, 6, 2)>,
+				<RA_PSEL(RA_PSEL_SCI_9, 1, 10)>,
+				<RA_PSEL(RA_PSEL_SCI_9, 6, 3)>,
+				<RA_PSEL(RA_PSEL_SCI_9, 6, 4)>;
+		};
+	};
+
+	sci5_default: sci5_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_5, 8, 5)>,
+				<RA_PSEL(RA_PSEL_SCI_5, 5, 13)>,
+				<RA_PSEL(RA_PSEL_SCI_5, 5, 8)>,
+				<RA_PSEL(RA_PSEL_SCI_5, 5, 0)>;
+		};
+	};
+
+	sci6_default: sci6_default {
+		group1 {
+			/* tx rx */
+			psels = <RA_PSEL(RA_PSEL_SCI_5, 8, 5)>,
+				<RA_PSEL(RA_PSEL_SCI_5, 5, 13)>,
+				<RA_PSEL(RA_PSEL_SCI_5, 5, 8)>,
+				<RA_PSEL(RA_PSEL_SCI_5, 5, 0)>;
+		};
+	};
+
+	sci8_default: sci8_default {
+		group1 {
+			/* tx rx rts cts - BLE */
+			psels = <RA_PSEL(RA_PSEL_SCI_8, 10, 0)>,
+				<RA_PSEL(RA_PSEL_SCI_8, 6, 7)>,
+				<RA_PSEL(RA_PSEL_SCI_8, 6, 6)>,
+				<RA_PSEL(RA_PSEL_SCI_8, 8, 1)>;
+		};
+	};
+
+	iic1_default: iic1_default {
+		group1 {
+			/* SCL1 SDA1 */
+			psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,
+			<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
+			drive-strength = "medium";
+		};
+	};
+
+	spi1_default: spi1_default {
+		group1 {
+			/* MISO MOSI RSPCK SSL0 SSL1 */
+			psels = <RA_PSEL(RA_PSEL_SPI, 1, 0)>,
+			<RA_PSEL(RA_PSEL_SPI, 1, 1)>,
+			<RA_PSEL(RA_PSEL_SPI, 1, 2)>,
+			<RA_PSEL(RA_PSEL_SPI, 1, 3)>,
+			<RA_PSEL(RA_PSEL_SPI, 1, 4)>;
+		};
+	};
+
+	usbhs_default: usbhs_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_USBHS, 11, 1)>; /* USBHS-VBUS */
+			drive-strength = "high";
+		};
+	};
+
+	adc0_default: adc0_default {
+		group1 {
+			/* input */
+			psels = <RA_PSEL(RA_PSEL_ADC, 0, 6)>,
+				<RA_PSEL(RA_PSEL_ADC, 0, 5)>,
+				<RA_PSEL(RA_PSEL_ADC, 0, 4)>,
+				<RA_PSEL(RA_PSEL_ADC, 0, 2)>,
+				<RA_PSEL(RA_PSEL_ADC, 0, 1)>,
+				<RA_PSEL(RA_PSEL_ADC, 0, 15)>,
+				<RA_PSEL(RA_PSEL_ADC, 0, 14)>,
+				<RA_PSEL(RA_PSEL_ADC, 0, 0)>;
+			renesas,analog-enable;
+		};
+	};
+
+	ether_default: ether_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_ETH_RMII, 2, 14)>, /* ET0_MDC */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 2, 11)>, /* ET0_MDIO */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 4, 5)>, /* RMII0_TXD_EN_B */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 4, 6)>, /* RMII0_TXD1_BR */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 7, 0)>, /* RMII0_TXD0_B */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 7, 1)>, /* REF50CK0_B */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 7, 2)>, /* RMII0_RXD0_B */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 7, 3)>, /* RMII0_RXD1_B */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 7, 4)>, /* RMII0_RX_ER_B */
+				<RA_PSEL(RA_PSEL_ETH_RMII, 7, 5)>; /* RMII0_CRS_DV_B */
+			drive-strength = "high";
+		};
+	};
+
+	pwm1_default: pwm1_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 5)>;
+		};
+	};
+
+	pwm3_default: pwm3_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 11)>;
+		};
+	};
+
+	pwm4_default: pwm4_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_GPT1, 6, 8)>;
+		};
+	};
+
+	pwm6_default: pwm6_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_GPT1, 6, 0)>,
+				<RA_PSEL(RA_PSEL_GPT1, 6, 1)>;
+		};
+	};
+
+	pwm7_default: pwm7_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_GPT1, 3, 3)>;
+		};
+	};
+
+	pwm8_default: pwm8_default {
+		group1 {
+			psels = <RA_PSEL(RA_PSEL_GPT1, 1, 6)>,
+				<RA_PSEL(RA_PSEL_GPT1, 6, 5)>;
+		};
+	};
+};