arch: arm: cortex_m: Implement USE_SWITCH support for armv8-m.mainline (and some other changes)

arch/arm/core/Kconfig

@@ -6,14 +6,14 @@
 config CPU_CORTEX_M
 	bool
 	select CPU_CORTEX
-	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN
+	select ARCH_HAS_CUSTOM_SWAP_TO_MAIN if !USE_SWITCH
 	select HAS_CMSIS_CORE
 	select HAS_FLASH_LOAD_OFFSET
 	select ARCH_HAS_SINGLE_THREAD_SUPPORT
 	select ARCH_HAS_THREAD_ABORT
 	select ARCH_HAS_TRUSTED_EXECUTION if ARM_TRUSTZONE_M
 	select ARCH_HAS_STACK_PROTECTION if (ARM_MPU && !ARMV6_M_ARMV8_M_BASELINE) || CPU_CORTEX_M_HAS_SPLIM
-	select ARCH_HAS_USERSPACE if ARM_MPU
+	select ARCH_HAS_USERSPACE if ARM_MPU && !USE_SWITCH
 	select ARCH_HAS_NOCACHE_MEMORY_SUPPORT if ARM_MPU && CPU_HAS_ARM_MPU && CPU_HAS_DCACHE
 	select ARCH_HAS_RAMFUNC_SUPPORT
 	select ARCH_HAS_NESTED_EXCEPTION_DETECTION

arch/arm/core/cortex_m/CMakeLists.txt

@@ -11,12 +11,14 @@ zephyr_library_sources(
   scb.c
   thread_abort.c
   vector_table.S
-  swap_helper.S
   irq_manage.c
   prep_c.c
   thread.c
-  cpu_idle.c
-  )
+  cpu_idle.c)
+
+zephyr_library_sources_ifdef(CONFIG_USE_SWITCH switch.S)
+
+zephyr_library_sources_ifndef(CONFIG_USE_SWITCH swap_helper.S)
 
 zephyr_library_sources_ifndef(CONFIG_ARM_CUSTOM_INTERRUPT_CONTROLLER irq_init.c)
 zephyr_library_sources_ifdef(CONFIG_GEN_SW_ISR_TABLE isr_wrapper.c)
@@ -32,32 +34,26 @@ if(CONFIG_NULL_POINTER_EXCEPTION_DETECTION_DWT)
 endif()
 
 if(CONFIG_CORTEX_M_DWT)
-	if (CONFIG_TIMING_FUNCTIONS)
-		zephyr_library_sources(timing.c)
-	endif()
-endif()
-
-if (CONFIG_SW_VECTOR_RELAY)
-if (CONFIG_CPU_CORTEX_M_HAS_VTOR)
-  set(relay_vector_table_sort_key relay_vectors)
-else()
-# Using 0x0 prefix will result in placing the relay vector table section
-# at the beginning of ROM_START (i.e before other sections in ROM_START);
-# required for CPUs without VTOR, which need to have the exception vector
-# table starting at a fixed address at the beginning of ROM.
-  set(relay_vector_table_sort_key 0x0relay_vectors)
+  if(CONFIG_TIMING_FUNCTIONS)
+    zephyr_library_sources(timing.c)
+  endif()
 endif()
 
-zephyr_linker_sources(
-  ROM_START
-  SORT_KEY ${relay_vector_table_sort_key}
-  relay_vector_table.ld
-  )
+if(CONFIG_SW_VECTOR_RELAY)
+  if(CONFIG_CPU_CORTEX_M_HAS_VTOR)
+    set(relay_vector_table_sort_key relay_vectors)
+  else()
+    # Using 0x0 prefix will result in placing the relay vector table section at
+    # the beginning of ROM_START (i.e before other sections in ROM_START);
+    # required for CPUs without VTOR, which need to have the exception vector
+    # table starting at a fixed address at the beginning of ROM.
+    set(relay_vector_table_sort_key 0x0relay_vectors)
+  endif()
+
+  zephyr_linker_sources(ROM_START SORT_KEY ${relay_vector_table_sort_key}
+                        relay_vector_table.ld)
 endif()
 
-if (CONFIG_SW_VECTOR_RELAY OR CONFIG_SW_VECTOR_RELAY_CLIENT)
-zephyr_linker_sources(
-  RAM_SECTIONS
-  vt_pointer_section.ld
-  )
+if(CONFIG_SW_VECTOR_RELAY OR CONFIG_SW_VECTOR_RELAY_CLIENT)
+  zephyr_linker_sources(RAM_SECTIONS vt_pointer_section.ld)
 endif()

arch/arm/core/cortex_m/Kconfig

@@ -234,6 +234,7 @@ config ARMV8_M_MAINLINE
 	select ARMV7_M_ARMV8_M_MAINLINE
 	select CPU_CORTEX_M_HAS_SPLIM
 	select CPU_CORTEX_M_HAS_CMSE
+	select USE_SWITCH_SUPPORTED
 	help
 	  This option signifies the use of an ARMv8-M processor
 	  implementation, supporting the Main Extension.

arch/arm/core/cortex_m/cmse/arm_core_cmse.c

@@ -9,7 +9,7 @@
 
 int arm_cmse_mpu_region_get(uint32_t addr)
 {
-	cmse_address_info_t addr_info =	cmse_TT((void *)addr);
+	cmse_address_info_t addr_info = cmse_TT((void *)addr);
 
 	if (addr_info.flags.mpu_region_valid) {
 		return addr_info.flags.mpu_region;
@@ -40,8 +40,7 @@ int arm_cmse_addr_readwrite_ok(uint32_t addr, int force_npriv)
 	return arm_cmse_addr_read_write_ok(addr, force_npriv, 1);
 }
 
-static int arm_cmse_addr_range_read_write_ok(uint32_t addr, uint32_t size,
-	int force_npriv, int rw)
+static int arm_cmse_addr_range_read_write_ok(uint32_t addr, uint32_t size, int force_npriv, int rw)
 {
 	int flags = 0;
 
@@ -74,18 +73,18 @@ int arm_cmse_addr_range_readwrite_ok(uint32_t addr, uint32_t size, int force_npr
 
 int arm_cmse_mpu_nonsecure_region_get(uint32_t addr)
 {
-	cmse_address_info_t addr_info =	cmse_TTA((void *)addr);
+	cmse_address_info_t addr_info = cmse_TTA((void *)addr);
 
 	if (addr_info.flags.mpu_region_valid) {
-		return  addr_info.flags.mpu_region;
+		return addr_info.flags.mpu_region;
 	}
 
 	return -EINVAL;
 }
 
 int arm_cmse_sau_region_get(uint32_t addr)
 {
-	cmse_address_info_t addr_info =	cmse_TT((void *)addr);
+	cmse_address_info_t addr_info = cmse_TT((void *)addr);
 
 	if (addr_info.flags.sau_region_valid) {
 		return addr_info.flags.sau_region;
@@ -96,7 +95,7 @@ int arm_cmse_sau_region_get(uint32_t addr)
 
 int arm_cmse_idau_region_get(uint32_t addr)
 {
-	cmse_address_info_t addr_info =	cmse_TT((void *)addr);
+	cmse_address_info_t addr_info = cmse_TT((void *)addr);
 
 	if (addr_info.flags.idau_region_valid) {
 		return addr_info.flags.idau_region;
@@ -107,13 +106,12 @@ int arm_cmse_idau_region_get(uint32_t addr)
 
 int arm_cmse_addr_is_secure(uint32_t addr)
 {
-	cmse_address_info_t addr_info =	cmse_TT((void *)addr);
+	cmse_address_info_t addr_info = cmse_TT((void *)addr);
 
 	return addr_info.flags.secure;
 }
 
-static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr,
-	int force_npriv, int rw)
+static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr, int force_npriv, int rw)
 {
 	cmse_address_info_t addr_info;
 	if (force_npriv) {
@@ -122,8 +120,7 @@ static int arm_cmse_addr_nonsecure_read_write_ok(uint32_t addr,
 		addr_info = cmse_TTA((void *)addr);
 	}
 
-	return rw ? addr_info.flags.nonsecure_readwrite_ok :
-		addr_info.flags.nonsecure_read_ok;
+	return rw ? addr_info.flags.nonsecure_readwrite_ok : addr_info.flags.nonsecure_read_ok;
 }
 
 int arm_cmse_addr_nonsecure_read_ok(uint32_t addr, int force_npriv)
@@ -137,7 +134,7 @@ int arm_cmse_addr_nonsecure_readwrite_ok(uint32_t addr, int force_npriv)
 }
 
 static int arm_cmse_addr_range_nonsecure_read_write_ok(uint32_t addr, uint32_t size,
-	int force_npriv, int rw)
+						       int force_npriv, int rw)
 {
 	int flags = CMSE_NONSECURE;
 
@@ -156,18 +153,14 @@ static int arm_cmse_addr_range_nonsecure_read_write_ok(uint32_t addr, uint32_t s
 	}
 }
 
-int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size,
-	int force_npriv)
+int arm_cmse_addr_range_nonsecure_read_ok(uint32_t addr, uint32_t size, int force_npriv)
 {
-	return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size,
-		force_npriv, 0);
+	return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size, force_npriv, 0);
 }
 
-int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size,
-	int force_npriv)
+int arm_cmse_addr_range_nonsecure_readwrite_ok(uint32_t addr, uint32_t size, int force_npriv)
 {
-	return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size,
-		force_npriv, 1);
+	return arm_cmse_addr_range_nonsecure_read_write_ok(addr, size, force_npriv, 1);
 }
 
 #endif /* CONFIG_ARM_SECURE_FIRMWARE */

arch/arm/core/cortex_m/coredump.c

@@ -7,31 +7,31 @@
 #include <string.h>
 #include <zephyr/debug/coredump.h>
 
-#define ARCH_HDR_VER			2
+#define ARCH_HDR_VER 2
 
 uint32_t z_arm_coredump_fault_sp;
 
 struct arm_arch_block {
 	struct {
-		uint32_t	r0;
-		uint32_t	r1;
-		uint32_t	r2;
-		uint32_t	r3;
-		uint32_t	r12;
-		uint32_t	lr;
-		uint32_t	pc;
-		uint32_t	xpsr;
-		uint32_t	sp;
+		uint32_t r0;
+		uint32_t r1;
+		uint32_t r2;
+		uint32_t r3;
+		uint32_t r12;
+		uint32_t lr;
+		uint32_t pc;
+		uint32_t xpsr;
+		uint32_t sp;
 
 		/* callee registers - optionally collected in V2 */
-		uint32_t	r4;
-		uint32_t	r5;
-		uint32_t	r6;
-		uint32_t	r7;
-		uint32_t	r8;
-		uint32_t	r9;
-		uint32_t	r10;
-		uint32_t	r11;
+		uint32_t r4;
+		uint32_t r5;
+		uint32_t r6;
+		uint32_t r7;
+		uint32_t r8;
+		uint32_t r9;
+		uint32_t r10;
+		uint32_t r11;
 	} r;
 } __packed;
 
@@ -76,12 +76,12 @@ void arch_coredump_info_dump(const struct arch_esf *esf)
 
 #if defined(CONFIG_EXTRA_EXCEPTION_INFO)
 	if (esf->extra_info.callee) {
-		arch_blk.r.r4  = esf->extra_info.callee->v1;
-		arch_blk.r.r5  = esf->extra_info.callee->v2;
-		arch_blk.r.r6  = esf->extra_info.callee->v3;
-		arch_blk.r.r7  = esf->extra_info.callee->v4;
-		arch_blk.r.r8  = esf->extra_info.callee->v5;
-		arch_blk.r.r9  = esf->extra_info.callee->v6;
+		arch_blk.r.r4 = esf->extra_info.callee->v1;
+		arch_blk.r.r5 = esf->extra_info.callee->v2;
+		arch_blk.r.r6 = esf->extra_info.callee->v3;
+		arch_blk.r.r7 = esf->extra_info.callee->v4;
+		arch_blk.r.r8 = esf->extra_info.callee->v5;
+		arch_blk.r.r9 = esf->extra_info.callee->v6;
 		arch_blk.r.r10 = esf->extra_info.callee->v7;
 		arch_blk.r.r11 = esf->extra_info.callee->v8;
 	}

arch/arm/core/cortex_m/cpu_idle.c

@@ -30,27 +30,31 @@ void z_arm_cpu_idle_init(void)
 #if defined(CONFIG_ARM_ON_EXIT_CPU_IDLE)
 #define ON_EXIT_IDLE_HOOK SOC_ON_EXIT_CPU_IDLE
 #else
-#define ON_EXIT_IDLE_HOOK do {} while (false)
+#define ON_EXIT_IDLE_HOOK                                                                          \
+	do {                                                                                       \
+	} while (false)
 #endif
 
 #if defined(CONFIG_ARM_ON_ENTER_CPU_IDLE_HOOK)
-#define SLEEP_IF_ALLOWED(wait_instr) do { \
-	/* Skip the wait instr if on_enter_cpu_idle returns false */ \
-	if (z_arm_on_enter_cpu_idle()) { \
-		/* Wait for all memory transaction to complete */ \
-		/* before entering low power state. */ \
-		__DSB(); \
-		wait_instr(); \
-		/* Inline the macro provided by SoC-specific code */ \
-		ON_EXIT_IDLE_HOOK; \
-	} \
-} while (false)
+#define SLEEP_IF_ALLOWED(wait_instr)                                                               \
+	do {                                                                                       \
+		/* Skip the wait instr if on_enter_cpu_idle returns false */                       \
+		if (z_arm_on_enter_cpu_idle()) {                                                   \
+			/* Wait for all memory transaction to complete */                          \
+			/* before entering low power state. */                                     \
+			__DSB();                                                                   \
+			wait_instr();                                                              \
+			/* Inline the macro provided by SoC-specific code */                       \
+			ON_EXIT_IDLE_HOOK;                                                         \
+		}                                                                                  \
+	} while (false)
 #else
-#define SLEEP_IF_ALLOWED(wait_instr) do { \
-	__DSB(); \
-	wait_instr(); \
-	ON_EXIT_IDLE_HOOK; \
-} while (false)
+#define SLEEP_IF_ALLOWED(wait_instr)                                                               \
+	do {                                                                                       \
+		__DSB();                                                                           \
+		wait_instr();                                                                      \
+		ON_EXIT_IDLE_HOOK;                                                                 \
+	} while (false)
 #endif
 
 #ifndef CONFIG_ARCH_HAS_CUSTOM_CPU_IDLE

arch/arm/core/cortex_m/debug.c

@@ -35,7 +35,7 @@ bool z_arm_debug_monitor_event_error_check(void)
 			printk("Null-pointer exception?\n");
 		}
 		__ASSERT((DWT->FUNCTION0 & DWT_FUNCTION_MATCHED_Msk) == 0,
-			"MATCHED flag should have been cleared on read.");
+			 "MATCHED flag should have been cleared on read.");
 
 		return true;
 	}
@@ -55,8 +55,8 @@ bool z_arm_debug_monitor_event_error_check(void)
  * so we add a build assert that catches it.
  */
 BUILD_ASSERT(!(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE &
-	(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1)),
-	"the size of the partition must be power of 2");
+	       (CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1)),
+	     "the size of the partition must be power of 2");
 
 int z_arm_debug_enable_null_pointer_detection(void)
 {
@@ -81,20 +81,12 @@ int z_arm_debug_enable_null_pointer_detection(void)
 	DWT->COMP0 = 0;
 	DWT->COMP1 = CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1;
 
-	DWT->FUNCTION0 =
-		((0x4 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk)
-		|
-		((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk)
-		|
-		((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk)
-		;
-	DWT->FUNCTION1 =
-		((0x7 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk)
-		|
-		((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk)
-		|
-		((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk)
-		;
+	DWT->FUNCTION0 = ((0x4 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk) |
+			 ((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk) |
+			 ((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk);
+	DWT->FUNCTION1 = ((0x7 << DWT_FUNCTION_MATCH_Pos) & DWT_FUNCTION_MATCH_Msk) |
+			 ((0x1 << DWT_FUNCTION_ACTION_Pos) & DWT_FUNCTION_ACTION_Msk) |
+			 ((0x0 << DWT_FUNCTION_DATAVSIZE_Pos) & DWT_FUNCTION_DATAVSIZE_Msk);
 #elif defined(CONFIG_ARMV7_M_ARMV8_M_MAINLINE)
 
 	/* ASSERT that we have the comparator needed for the implementation */
@@ -106,13 +98,10 @@ int z_arm_debug_enable_null_pointer_detection(void)
 	/* Use comparator 0, R/W access check */
 	DWT->COMP0 = 0;
 
-	DWT->FUNCTION0 = (0x7 << DWT_FUNCTION_FUNCTION_Pos) &
-		DWT_FUNCTION_FUNCTION_Msk;
-
+	DWT->FUNCTION0 = (0x7 << DWT_FUNCTION_FUNCTION_Pos) & DWT_FUNCTION_FUNCTION_Msk;
 
 	/* Set mask according to the desired size */
-	DWT->MASK0 = 32 - __builtin_clzl(
-		CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1);
+	DWT->MASK0 = 32 - __builtin_clzl(CONFIG_CORTEX_M_NULL_POINTER_EXCEPTION_PAGE_SIZE - 1);
 #endif
 
 	return 0;