Update arm branch to master

.shippable.yml

@@ -27,6 +27,7 @@ build:
     ci:
       - export CCACHE_DIR=${SHIPPABLE_BUILD_DIR}/ccache/.ccache
       - export COMMIT_RANGE=${SHIPPABLE_COMMIT_RANGE}
+      - echo ${SHIPPABLE_COMMIT_RANGE}
       - source zephyr-env.sh
       - ccache -s --max-size=2000M
       - make host-tools

arch/arm/core/isr_wrapper.S

@@ -43,6 +43,10 @@ SECTION_FUNC(TEXT, _isr_wrapper)
 
 	push {lr}		/* lr is now the first item on the stack */
 
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+	bl read_systick_start_of_isr
+#endif
+
 #ifdef CONFIG_KERNEL_EVENT_LOGGER_INTERRUPT
 	bl _sys_k_event_logger_interrupt
 #endif
@@ -105,6 +109,20 @@ _idle_state_cleared:
 			 * in thumb mode */
 
 	ldm r1!,{r0,r3}	/* arg in r0, ISR in r3 */
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+#if defined(CONFIG_ARMV6_M)
+	push {r3}
+#endif
+	push {lr}
+	bl read_systick_end_of_isr
+#if defined(CONFIG_ARMV6_M)
+	pop {r3}
+	mov lr,r3
+	pop {r3}
+#else
+	pop {lr}
+#endif
+#endif
 	blx r3		/* call ISR */
 
 #if defined(CONFIG_ARMV6_M)

arch/arm/core/swap.S

@@ -177,6 +177,23 @@ _thread_irq_disabled:
 
     msr PSP, ip
 
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+#if defined(CONFIG_ARMV6_M)
+    push {r3}
+#endif
+    push {lr}
+
+    bl read_systick_end_of_swap
+
+#if defined(CONFIG_ARMV6_M)
+    pop {r3}
+    mov lr,r3
+    pop {r3}
+#else
+    pop {lr}
+#endif
+#endif
+
     /* exc return */
     bx lr
 
@@ -292,6 +309,20 @@ _oops:
 
 SECTION_FUNC(TEXT, __swap)
 
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+#if defined(CONFIG_ARMV6_M)
+    push {r3}
+#endif
+    push {lr}
+    bl read_systick_start_of_swap
+#if defined(CONFIG_ARMV6_M)
+    pop {r3}
+    mov lr,r3
+    pop {r3}
+#else
+    pop {lr}
+#endif
+#endif
     ldr r1, =_kernel
     ldr r2, [r1, #_kernel_offset_to_current]
     str r0, [r2, #_thread_offset_to_basepri]

arch/arm/soc/arm/mps2/soc_devices.h

@@ -58,6 +58,13 @@
 #define CMSDK_APB_DUALTIMER_IRQ	IRQ_DUAL_TIMER
 #endif /* CONFIG_COUNTER */
 
+#if defined(CONFIG_I2C_SBCON)
+#define I2C_SBCON_0_BASE_ADDR	I2C_TOUCH_BASE_ADDR
+#define I2C_SBCON_1_BASE_ADDR	I2C_AUDIO_CONF_BASE_ADDR
+#define I2C_SBCON_2_BASE_ADDR	I2C_SHIELD0_BASE_ADDR
+#define I2C_SBCON_3_BASE_ADDR	I2C_SHIELD1_BASE_ADDR
+#endif
+
 #ifndef _ASMLANGUAGE
 
 #include "soc_registers.h"

arch/arm/soc/arm/mps2/soc_memory_map.h

@@ -35,6 +35,10 @@
 #define UART_4_BASE_ADDR	(MPS2_APB_BASE_ADDR + 0x9000)
 
 /* MPS2 peripherals in FPGA APB subsystem  */
-#define FPGAIO_BASE_ADDR	(MPS2_FPGA_APB_BASE_ADDR + 0x8000)
+#define I2C_TOUCH_BASE_ADDR	 (MPS2_FPGA_APB_BASE_ADDR + 0x2000)
+#define I2C_AUDIO_CONF_BASE_ADDR (MPS2_FPGA_APB_BASE_ADDR + 0x3000)
+#define FPGAIO_BASE_ADDR	 (MPS2_FPGA_APB_BASE_ADDR + 0x8000)
+#define I2C_SHIELD0_BASE_ADDR	 (MPS2_FPGA_APB_BASE_ADDR + 0x9000)
+#define I2C_SHIELD1_BASE_ADDR	 (MPS2_FPGA_APB_BASE_ADDR + 0xa000)
 
 #endif /* _SOC_MEMORY_MAP_H_ */

arch/arm/soc/atmel_sam/Kconfig

@@ -4,10 +4,5 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-config SOC_ATMEL_SAM3
-	bool
-	depends on ARM
-	default n
-
 # Select SoC Part No. and configuration options
 source "arch/arm/soc/atmel_sam/*/Kconfig.soc"

arch/arm/soc/atmel_sam/Kconfig.defconfig

@@ -16,7 +16,7 @@ config SOC_FAMILY
 	default atmel_sam
 
 config WATCHDOG
-	def_bool y if !SOC_ATMEL_SAM3X8E
+	def_bool y
 
 endif #SOC_FAMILY_SAM
 

arch/arm/soc/atmel_sam/sam3x/Kconfig.defconfig.series

@@ -6,15 +6,15 @@
 # SPDX-License-Identifier: Apache-2.0
 #
 
-if SOC_SERIES_SAM3X || SOC_ATMEL_SAM3X8E
+if SOC_SERIES_SAM3X
 
 config SOC_SERIES
 	string
 	default sam3x
 
 config SOC_PART_NUMBER
 	string
-	default sam3x8e if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E
+	default sam3x8e if SOC_PART_NUMBER_SAM3X8E
 
 config NUM_IRQ_PRIO_BITS
 	int
@@ -42,66 +42,19 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 # to provide one continuous 96K block.
 #
 config SRAM_SIZE
-	default 96 if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E
+	default 96 if SOC_PART_NUMBER_SAM3X8E
 
 config SRAM_BASE_ADDRESS
-	default 0x20000000 if !SOC_PART_NUMBER_SAM3X8E && !SOC_ATMEL_SAM3X8E
-	default 0x20070000 if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E
+	default 0x20000000 if !SOC_PART_NUMBER_SAM3X8E
+	default 0x20070000 if SOC_PART_NUMBER_SAM3X8E
 
 #
 # Atmel SAM3X family has flash starting @ 0x00080000.
 #
 config FLASH_SIZE
-	default 512 if SOC_PART_NUMBER_SAM3X8E || SOC_ATMEL_SAM3X8E
+	default 512 if SOC_PART_NUMBER_SAM3X8E
 
 config FLASH_BASE_ADDRESS
 	default 0x00080000
 
-if UART_ATMEL_SAM3
-
-config UART_ATMEL_SAM3_BAUD_RATE
-	default 115200
-
-config UART_ATMEL_SAM3_CLK_FREQ
-	default 84000000
-
-endif # UART_ATMEL_SAM3
-
-if GPIO
-
-config GPIO_ATMEL_SAM3
-	def_bool y
-
-config GPIO_ATMEL_SAM3_PORTA
-	default y
-
-config GPIO_ATMEL_SAM3_PORTB
-	default y
-
-config GPIO_ATMEL_SAM3_PORTC
-	default y
-
-config GPIO_ATMEL_SAM3_PORTD
-	default y
-
-endif # GPIO
-
-if I2C
-
-config I2C_ATMEL_SAM3
-	def_bool y
-
-config I2C_0
-	default y
-config I2C_0_IRQ_PRI
-	default 0
-
-config I2C_1
-	default y
-
-config I2C_1_IRQ_PRI
-	default 0
-
-endif # I2C
-
 endif # SOC_SERIES_SAM3X

arch/arm/soc/atmel_sam/sam3x/Kconfig.series

@@ -16,13 +16,3 @@ config SOC_SERIES_SAM3X
 	help
 	  Enable support for Atmel SAM3X Cortex-M3 microcontrollers.
 	  Part No.: SAM3X8E
-
-config SOC_ATMEL_SAM3X8E
-	bool "Atmel SAM3X8E Processor"
-	select SOC_PART_NUMBER_SAM3X8E
-	select CPU_CORTEX_M
-	select CPU_CORTEX_M3
-	select SOC_FAMILY_SAM
-	select SYS_POWER_LOW_POWER_STATE_SUPPORTED
-	select CPU_HAS_SYSTICK
-	select SOC_ATMEL_SAM3

arch/arm/soc/atmel_sam/sam3x/Kconfig.soc

@@ -15,7 +15,7 @@ choice
 		bool "SAM3X8E"
 endchoice
 
-if SOC_SERIES_SAM3X || SOC_ATMEL_SAM3X8E
+if SOC_SERIES_SAM3X
 
 config SOC_ATMEL_SAM3X_EXT_SLCK
 	bool "Atmel SAM3 to use external crystal oscillator for slow clock"
@@ -75,7 +75,7 @@ config SOC_ATMEL_SAM3X_PLLA_DIVA
 
 config SOC_ATMEL_SAM3X_WAIT_MODE
 	bool "Atmel SAM3 goes to Wait mode instead of Sleep mode"
-	depends on SOC_ATMEL_SAM3_EXT_MAINCK
+	depends on SOC_ATMEL_SAM3X_EXT_MAINCK
 	default y if DEBUG
 	help
 	For JTAG debugging CPU clock (HCLK) should not stop. In order

arch/arm/soc/atmel_sam/sam3x/soc.c

@@ -50,7 +50,7 @@ static ALWAYS_INLINE void clock_init(void)
 	/* Wait for oscillator to be stablized */
 	while (!(__SUPC->sr & SUPC_SR_OSCSEL))
 		;
-#endif /* CONFIG_SOC_ATMEL_SAM3_EXT_SLCK */
+#endif /* CONFIG_SOC_ATMEL_SAM3X_EXT_SLCK */
 
 #ifdef CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK
 	/* Start the external main oscillator */
@@ -88,7 +88,7 @@ static ALWAYS_INLINE void clock_init(void)
 	/* Wait for main fast RC oscillator to be stablized */
 	while (!(__PMC->sr & PMC_INT_MOSCRCS))
 		;
-#endif /* CONFIG_SOC_ATMEL_SAM3_EXT_MAINCK */
+#endif /* CONFIG_SOC_ATMEL_SAM3X_EXT_MAINCK */
 
 	/* Use PLLA as master clock.
 	 * According to datasheet, PMC_MCKR must not be programmed in

arch/x86/core/intstub.S

@@ -78,6 +78,15 @@
  */
 SECTION_FUNC(TEXT, _interrupt_enter)
 
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+	pushl %eax
+	pushl %edx
+	rdtsc
+	mov %eax, __start_intr_tsc
+	mov %edx, __start_intr_tsc+4
+	pop %edx
+	pop %eax
+#endif
 	/*
 	 * The gen_idt tool creates an interrupt-gate descriptor for
 	 * all connections.  The processor will automatically clear the IF
@@ -246,6 +255,19 @@ alreadyOnIntStack:
 	 */
 	push	%eax
 #endif
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+	/* Save the eax and edx registers before reading the time stamp
+	* once done pop the values
+	*/
+	pushl %eax
+	pushl %edx
+	rdtsc
+	mov %eax,__end_intr_tsc
+	mov %edx,__end_intr_tsc+4
+	pop %edx
+	pop %eax
+#endif
+
 #ifdef CONFIG_NESTED_INTERRUPTS
 	sti			/* re-enable interrupts */
 #endif

arch/x86/core/swap.S

@@ -77,7 +77,28 @@
  *
  */
 
+.macro read_tsc var_name
+	push %eax
+	push %edx
+	rdtsc
+	mov %eax,\var_name
+	mov %edx,\var_name+4
+	pop %edx
+	pop %eax
+.endm
 SECTION_FUNC(TEXT, __swap)
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+	/* Save the eax and edx registers before reading the time stamp
+	* once done pop the values.
+	*/
+	push %eax
+	push %edx
+	rdtsc
+	mov %eax,__start_swap_tsc
+	mov %edx,__start_swap_tsc+4
+	pop %edx
+	pop %eax
+#endif
 #ifdef CONFIG_X86_IAMCU
 	/* save EFLAGS on stack right before return address, just as SYSV would
 	 * have done
@@ -335,5 +356,16 @@ skipIntLatencyStop:
 	 */
 	popl	%edx
 	movl	%edx, (%esp)
+#endif
+
+#ifdef CONFIG_EXECUTION_BENCHMARKING
+	/* Save the eax and edx registers before reading the time stamp
+	* once done pop the values.
+	*/
+	cmp $0x1,__read_swap_end_tsc_value
+	jne time_read_not_needed
+	movw $0x2,__read_swap_end_tsc_value
+	read_tsc __common_var_swap_end_tsc
+time_read_not_needed:
 #endif
 	ret

boards/arm/arduino_due/Kconfig.board

@@ -1,4 +1,9 @@
+# Kconfig - Arduino Due Board configuration
+#
+# Copyright (c) 2017 Justin Watson
+# SPDX-License-Identifier: Apache-2.0
+#
 
 config BOARD_ARDUINO_DUE
 	bool "Arduino Due Board"
-	depends on SOC_ATMEL_SAM3X8E
+	depends on SOC_PART_NUMBER_SAM3X8E