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Merged
merged 3 commits into from
Jul 6, 2018
Merged

drivers: add imx7d i2c driver #7424

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6ec7af0
drivers: add i.MX I2C driver shim
diegosueiro Jul 3, 2018
37e4660
arch: Add imx7d_m4 i2c definitions
diegosueiro May 11, 2018
84b5445
board: add i2c support for colibri_imx7d_m4 board
diegosueiro Jul 2, 2018
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7 changes: 7 additions & 0 deletions arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.defconfig.mcimx7_m4
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Expand Up @@ -43,6 +43,13 @@ config UART_IMX

endif # SERIAL

if I2C

config I2C_IMX
def_bool y

endif # I2C

config DOMAIN_ID
int
default 1
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1 change: 1 addition & 0 deletions arch/arm/soc/nxp_imx/mcimx7_m4/Kconfig.soc
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Expand Up @@ -13,6 +13,7 @@ config SOC_MCIMX7_M4
bool "SOC_MCIMX7_M4"
select HAS_IMX_HAL
select HAS_IMX_GPIO
select HAS_IMX_I2C

endchoice

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60 changes: 60 additions & 0 deletions arch/arm/soc/nxp_imx/mcimx7_m4/soc.c
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Expand Up @@ -99,6 +99,62 @@ static void nxp_mcimx7_uart_config(void)
}
#endif /* CONFIG_UART_IMX */


#ifdef CONFIG_I2C_IMX
static void nxp_mcimx7_i2c_config(void)
{

#ifdef CONFIG_I2C_1
/* In this example, we need to grasp board I2C exclusively */
RDC_SetPdapAccess(RDC, rdcPdapI2c1,
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
false, false);
/* Select I2C clock derived from OSC clock(24M) */
CCM_UpdateRoot(CCM, ccmRootI2c1, ccmRootmuxI2cOsc24m, 0, 0);
/* Enable I2C clock */
CCM_EnableRoot(CCM, ccmRootI2c1);
CCM_ControlGate(CCM, ccmCcgrGateI2c1, ccmClockNeededRunWait);
#endif /* CONFIG_I2C_1 */

#ifdef CONFIG_I2C_2
/* In this example, we need to grasp board I2C exclusively */
RDC_SetPdapAccess(RDC, rdcPdapI2c2,
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
false, false);
/* Select I2C clock derived from OSC clock(24M) */
CCM_UpdateRoot(CCM, ccmRootI2c2, ccmRootmuxI2cOsc24m, 0, 0);
/* Enable I2C clock */
CCM_EnableRoot(CCM, ccmRootI2c2);
CCM_ControlGate(CCM, ccmCcgrGateI2c2, ccmClockNeededRunWait);
#endif /* CONFIG_I2C_2 */

#ifdef CONFIG_I2C_3
/* In this example, we need to grasp board I2C exclusively */
RDC_SetPdapAccess(RDC, rdcPdapI2c3,
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
false, false);
/* Select I2C clock derived from OSC clock(24M) */
CCM_UpdateRoot(CCM, ccmRootI2c3, ccmRootmuxI2cOsc24m, 0, 0);
/* Enable I2C clock */
CCM_EnableRoot(CCM, ccmRootI2c3);
CCM_ControlGate(CCM, ccmCcgrGateI2c3, ccmClockNeededRunWait);
#endif /* CONFIG_I2C_3 */

#ifdef CONFIG_I2C_4
/* In this example, we need to grasp board I2C exclusively */
RDC_SetPdapAccess(RDC, rdcPdapI2c4,
RDC_DOMAIN_PERM(CONFIG_DOMAIN_ID, RDC_DOMAIN_PERM_RW),
false, false);
/* Select I2C clock derived from OSC clock(24M) */
CCM_UpdateRoot(CCM, ccmRootI2c4, ccmRootmuxI2cOsc24m, 0, 0);
/* Enable I2C clock */
CCM_EnableRoot(CCM, ccmRootI2c4);
CCM_ControlGate(CCM, ccmCcgrGateI2c4, ccmClockNeededRunWait);
#endif /* CONFIG_I2C_4 */

}
#endif /* CONFIG_I2C_IMX */

static int nxp_mcimx7_init(struct device *arg)
{
ARG_UNUSED(arg);
Expand All @@ -117,6 +173,10 @@ static int nxp_mcimx7_init(struct device *arg)
nxp_mcimx7_uart_config();
#endif /* CONFIG_UART_IMX */

#ifdef CONFIG_I2C_IMX
nxp_mcimx7_i2c_config();
#endif /* CONFIG_I2C_IMX */

return 0;
}

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1 change: 1 addition & 0 deletions boards/arm/colibri_imx7d_m4/Kconfig.board
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Expand Up @@ -9,3 +9,4 @@ config BOARD_COLIBRI_IMX7D_M4
bool "Toradex Colibri iMX7 Dual"
depends on SOC_SERIES_IMX7_M4
select SOC_PART_NUMBER_MCIMX7D5EVM10SC
select HAS_DTS_I2C_DEVICE
17 changes: 17 additions & 0 deletions boards/arm/colibri_imx7d_m4/Kconfig.defconfig
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Expand Up @@ -42,4 +42,21 @@ config UART_IMX_UART_2

endif # UART_IMX

if I2C_IMX

config I2C_1
def_bool n

config I2C_2
def_bool n

config I2C_3
def_bool n

config I2C_4
def_bool y

endif # I2C_IMX


endif # BOARD_COLIBRI_IMX7D_M4
5 changes: 5 additions & 0 deletions boards/arm/colibri_imx7d_m4/colibri_imx7d_m4.dts
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Expand Up @@ -18,6 +18,7 @@
uart-2 = &uart2;
led0 = &green_led;
sw0 = &user_switch_1;
i2c-4 = &i2c4;
};

chosen {
Expand Down Expand Up @@ -58,3 +59,7 @@
&gpio2 {
status = "ok";
};

&i2c4 {
status = "ok";
};
6 changes: 6 additions & 0 deletions boards/arm/colibri_imx7d_m4/doc/colibri_imx7d_m4.rst
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Expand Up @@ -82,6 +82,8 @@ supports the following hardware features on the Cortex M4 Core:
+-----------+------------+-------------------------------------+
| GPIO | on-chip | gpio |
+-----------+------------+-------------------------------------+
| I2C | on-chip | i2c |
+-----------+------------+-------------------------------------+
| UART | on-chip | serial port-polling; |
| | | serial port-interrupt |
+-----------+------------+-------------------------------------+
Expand Down Expand Up @@ -109,6 +111,10 @@ was tested with the following pinmux controller configuration.
+---------------+-----------------+---------------------------+
| SODIMM_133 | GPIO2_IO26 | SW0 |
+---------------+-----------------+---------------------------+
| SODIMM_194 | I2C4_SDA | I2C_SDA |
+---------------+-----------------+---------------------------+
| SODIMM_196 | I2C4_SCL | I2C_SCL |
+---------------+-----------------+---------------------------+

System Clock
============
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96 changes: 96 additions & 0 deletions boards/arm/colibri_imx7d_m4/pinmux.c
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Expand Up @@ -48,6 +48,102 @@ static int colibri_imx7d_m4_pinmux_init(struct device *dev)
IOMUXC_UART2_RX_DATA_SELECT_INPUT_DAISY(3);
#endif /* CONFIG_UART_IMX_UART_2 */

#ifdef CONFIG_I2C_1
IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL =
IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_I2C1_SCL_SION_MASK;
IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA =
IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_I2C1_SDA_SION_MASK;

IOMUXC_I2C1_SCL_SELECT_INPUT = IOMUXC_I2C1_SCL_SELECT_INPUT_DAISY(1);
IOMUXC_I2C1_SDA_SELECT_INPUT = IOMUXC_I2C1_SDA_SELECT_INPUT_DAISY(1);

IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL =
IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_I2C1_SCL_HYS_MASK;

IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA =
IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_I2C1_SDA_HYS_MASK;
#endif /* CONFIG_I2C_1 */

#ifdef CONFIG_I2C_2
IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL =
IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_I2C2_SCL_SION_MASK;
IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA =
IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_I2C2_SDA_SION_MASK;

IOMUXC_I2C2_SCL_SELECT_INPUT = IOMUXC_I2C2_SCL_SELECT_INPUT_DAISY(1);
IOMUXC_I2C2_SDA_SELECT_INPUT = IOMUXC_I2C2_SDA_SELECT_INPUT_DAISY(1);

IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL =
IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_I2C2_SCL_HYS_MASK;

IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA =
IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_I2C2_SDA_HYS_MASK;
#endif /* CONFIG_I2C_2 */

#ifdef CONFIG_I2C_3
IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL =
IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_I2C3_SCL_SION_MASK;
IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA =
IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_MUX_MODE(0) |
IOMUXC_SW_MUX_CTL_PAD_I2C3_SDA_SION_MASK;

IOMUXC_I2C3_SCL_SELECT_INPUT = IOMUXC_I2C3_SCL_SELECT_INPUT_DAISY(2);
IOMUXC_I2C3_SDA_SELECT_INPUT = IOMUXC_I2C3_SDA_SELECT_INPUT_DAISY(2);

IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL =
IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_I2C3_SCL_HYS_MASK;

IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA =
IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_PS(3) |
IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_I2C3_SDA_HYS_MASK;
#endif /* CONFIG_I2C_3 */

#ifdef CONFIG_I2C_4
IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2 =
IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD2_SION_MASK;
IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3 =
IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_MUX_MODE(3) |
IOMUXC_SW_MUX_CTL_PAD_ENET1_RGMII_TD3_SION_MASK;

IOMUXC_I2C4_SCL_SELECT_INPUT = IOMUXC_I2C4_SCL_SELECT_INPUT_DAISY(4);
IOMUXC_I2C4_SDA_SELECT_INPUT = IOMUXC_I2C4_SDA_SELECT_INPUT_DAISY(4);

IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2 =
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_PS(1) |
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD2_HYS_MASK;

IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3 =
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PE_MASK |
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_PS(1) |
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_DSE(0) |
IOMUXC_SW_PAD_CTL_PAD_ENET1_RGMII_TD3_HYS_MASK;
#endif /* CONFIG_I2C_4 */

return 0;

}
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1 change: 1 addition & 0 deletions drivers/i2c/CMakeLists.txt
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Expand Up @@ -6,6 +6,7 @@ zephyr_library_sources_ifdef(CONFIG_I2C_CC32XX i2c_cc32xx.c)
zephyr_library_sources_ifdef(CONFIG_I2C_DW i2c_dw.c)
zephyr_library_sources_ifdef(CONFIG_I2C_ESP32 i2c_esp32.c)
zephyr_library_sources_ifdef(CONFIG_I2C_GPIO i2c_gpio.c)
zephyr_library_sources_ifdef(CONFIG_I2C_IMX i2c_imx.c)
zephyr_library_sources_ifdef(CONFIG_I2C_MCUX i2c_mcux.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_TWI i2c_nrfx_twi.c)
zephyr_library_sources_ifdef(CONFIG_NRFX_TWIM i2c_nrfx_twim.c)
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7 changes: 7 additions & 0 deletions drivers/i2c/Kconfig
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Expand Up @@ -202,6 +202,13 @@ config I2C_MCUX
help
Enable the mcux I2C driver.

config I2C_IMX
bool "i.MX I2C driver"
depends on HAS_IMX_I2C
select HAS_DTS_I2C
help
Enable the i.MX I2C driver.

config I2C_CC32XX
bool "CC32XX I2C driver"
depends on SOC_SERIES_CC32XX
Expand Down
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