Add TI J721e R5 and BeagleBone AI64 R5 initial support

boards/arm/beagle_bbai64_r5/Kconfig.board

@@ -0,0 +1,9 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_BBAI64_R5
+	bool "BeagleBone AI-64"
+	depends on SOC_TI_J721E_R5
+	select CPU_CORTEX_R5

boards/arm/beagle_bbai64_r5/Kconfig.defconfig

@@ -0,0 +1,11 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_BBAI64_R5
+
+config BOARD
+	default "beagle_bbai64_r5"
+
+endif # BOARD_BBAI64_R5

boards/arm/beagle_bbai64_r5/beagle_bbai64_r5.dts

@@ -0,0 +1,29 @@
+/* Copyright (C) 2023 BeagleBoard.org Foundation
+ * Copyright (C) 2023 S Prashanth
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+
+#include <ti/j721e_r5.dtsi>
+#include <arm/ti/j721e-pinctrl.dtsi>
+#include <freq.h>
+
+/ {
+	chosen {
+		zephyr,sram = &atcm;
+		zephyr,console = &uart2;
+	};
+};
+
+&uart2 {
+	current-speed = <115200>;
+	status = "okay";
+	pinctrl-0 = <&uart2_tx_default &uart2_rx_default>;
+	pinctrl-names = "default";
+};
+
+&systick_timer {
+	status = "okay";
+};

boards/arm/beagle_bbai64_r5/beagle_bbai64_r5.yaml

@@ -0,0 +1,16 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+identifier: beagle_bbai64_r5
+name: BeagleBone-AI64
+type: mcu
+arch: arm
+ram: 32
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+supported:
+  - uart

boards/arm/beagle_bbai64_r5/beagle_bbai64_r5_defconfig

@@ -0,0 +1,20 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_SOC_SERIES_TI_J721E=y
+CONFIG_SOC_TI_J721E_R5=y
+
+# enable uart
+CONFIG_SERIAL=y
+
+# enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+CONFIG_BUILD_OUTPUT_UF2=n
+
+CONFIG_XIP=n
+
+CONFIG_OPENAMP_RSC_TABLE=y

boards/arm/beagle_bbai64_r5/board.cmake

@@ -0,0 +1,4 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0

boards/arm/beagle_bbai64_r5/doc/index.rst

@@ -0,0 +1,90 @@
+.. _beaglebone_ai64:
+
+BeagleBone AI-64
+################
+
+Overview
+********
+BeagleBone AI-64 is a computational platform powered by TI J721E SoC, which is
+targeted for automotive applications.
+
+.. figure:: assets/bbai_64.png
+		:align: center
+		:width: 500px
+		:alt: BeagleBoard.org BeagleBone AI-64
+
+Hardware
+********
+The BeagleBone AI-64 is powered by TI J721E SoC, which has three domains (Main,
+MCU, WKUP). This document gives overview of Zephyr running on Cortex R5 in the
+Main domain.
+
+L1 Memory System
+----------------
+* 16 KB instruction cache.
+* 16 KB data cache.
+* 64 KB TCM.
+
+Region Address Translation
+--------------------------
+The RAT module performs a region based address translation. It translates a
+32-bit input address into a 48-bit output address. Any input transaction that
+starts inside of a programmed region will have its address translated, if the
+region is enabled.
+
+VIM Interrupt Controller
+------------------------
+The VIM aggregates device interrupts and sends them to the R5F CPU(s). The VIM
+module supports 512 interrupt inputs per R5F core. Each interrupt can be either
+a level or a pulse (both active-high). The VIM has two interrupt outputs per core
+IRQ and FIQ.
+
+Supported Features
+******************
+The board configuration supports,
+
++-----------+------------+----------------------+
+| Interface | Controller | Driver/Component     |
++===========+============+======================+
+| UART      | on-chip    | serial               |
++-----------+------------+----------------------+
+
+Other hardwares features are currently not supported.
+
+The default configuration can be found in the defconfig file.
+
+Flashing
+********
+The Zephyr image can be flashed to J721E Cortex R5 through remoteproc from
+Linux (Running on A72).
+
+Note:
+-----
+Use the latest Linux image from https://beagleboard.org/latest-images to bootup
+the BBAI-64. This is required for loading zephyr.elf/binary using remoteproc.
+
+Steps to flash the image
+------------------------
+The example shows how to load an image on Cortex R5FSS0_CORE0 on J721e.
+
+| Copy Zephyr image to the /lib/firmware/ directory.
+| ``cp build/zephyr/zephyr.elf /lib/firmware/``
+|
+| Ensure the Core is not running.
+| ``echo stop > /sys/class/remoteproc/remoteproc18/state``
+|
+| Configuring the image name to the remoteproc module.
+| ``echo zephyr.elf > /sys/class/remoteproc/remoteproc18/firmware``
+|
+| Once the image name is configured, send the start command.
+| ``echo start > /sys/class/remoteproc/remoteproc18/state``
+
+Console
+-------
+The Zephyr on BeagleBone AI-64 J721E Cortex R5 uses UART 2 (Rx p8.22, Tx p8.34)
+as console.
+
+References
+**********
+* `BeagleBone AI-64 Homepage <https://beagleboard.org/ai-64>`_
+* `J721E TRM <https://www.ti.com/lit/zip/spruil1>`_

dts/arm/ti/j721e-pinctrl.dtsi

@@ -0,0 +1,19 @@
+/* Copyright (C) 2023 BeagleBoard.org Foundation
+ * Copyright (C) 2023 S Prashanth
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h>
+
+&pinctrl {
+	uart2_tx_default: uart2_tx_default {
+		/* 0x1c is address of padconfig register of p8.34 and 14 is mux mode */
+		pinmux = <0x1c (PIN_OUTPUT | MUX_MODE_14)>;
+	};
+
+	uart2_rx_default: uart2_rx_default {
+		/* 0x14 is address of padconfig register of p8.22 and 14 is mux mode */
+		pinmux = <0x14 (PIN_INPUT | MUX_MODE_14)>;
+	};
+};

dts/arm/ti/j721e.dtsi

@@ -0,0 +1,41 @@
+/* Copyright (C) 2023 BeagleBoard.org Foundation
+ * Copyright (C) 2023 S Prashanth
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <freq.h>
+#include <arm/armv7-r.dtsi>
+#include <zephyr/dt-bindings/interrupt-controller/ti-vim.h>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	pinctrl: pinctrl@11c000 {
+		compatible = "ti,k3-pinctrl";
+		reg = <0x0011c000 0x2b4>;
+		status = "okay";
+	};
+
+	uart2: uart@2820000 {
+		compatible = "ns16550";
+		reg = <0x02820000 0x100>;
+		clock-frequency = <48000000>;
+		current-speed = <115200>;
+		interrupts = <0 160 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		reg-shift = <2>;
+		status = "disabled";
+	};
+
+	systick_timer: timer@24c0000 {
+		compatible = "ti,am654-dmtimer";
+		reg = <0x24c0000 0x70>;
+		reg-shift = <2>;
+		interrupts = <0 168 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
+		interrupt-parent = <&vim>;
+		status = "disabled";
+	};
+};

dts/arm/ti/j721e_r5.dtsi

@@ -0,0 +1,38 @@
+/* Copyright (C) 2023 BeagleBoard.org Foundation
+ * Copyright (C) 2023 S Prashanth
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/ti/j721e.dtsi>
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-r5";
+			reg = <0>;
+		};
+	};
+
+	soc {
+		atcm: memory@0 {
+			compatible = "mmio-sram";
+			reg = <0x00000000 DT_SIZE_K(32)>;
+		};
+
+		vim: interrupt-controller@ff80000 {
+			compatible = "ti,vim";
+			reg = <0x0ff80000 0x2800>;
+			interrupt-controller;
+			#interrupt-cells = <4>; /* {IRQ/FIQ, IRQ_NUM, IRQ_TYPE, IRQ_PRIO} */
+			status = "okay";
+		};
+	};
+};

include/zephyr/dt-bindings/pinctrl/ti-k3-pinctrl.h

@@ -39,6 +39,11 @@
 #define MUX_MODE_7		7
 #define MUX_MODE_8		8
 #define MUX_MODE_9		9
+#define MUX_MODE_10		10
+#define MUX_MODE_11		11
+#define MUX_MODE_12		12
+#define MUX_MODE_13		13
+#define MUX_MODE_14		14
 
 #define K3_PINMUX(offset, value, mux_mode)	(((offset) & 0x1fff)) ((value) | (mux_mode))
 

soc/arm/ti_k3/Kconfig

@@ -9,7 +9,6 @@ config SOC_FAMILY_TI_K3
 	bool
 
 if SOC_FAMILY_TI_K3
-
 config SOC_FAMILY
 	string
 	default "ti_k3"

soc/arm/ti_k3/j721e/CMakeLists.txt

@@ -0,0 +1,8 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+zephyr_library()
+
+zephyr_library_sources(soc.c)

soc/arm/ti_k3/j721e/Kconfig.defconfig

@@ -0,0 +1,11 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_TI_J721E_R5
+
+config SOC
+	default "j721e_r5"
+
+endif

soc/arm/ti_k3/j721e/Kconfig.defconfig.j721e_r5

@@ -0,0 +1,8 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+config SOC
+	default "j721e_r5"
+	depends on SOC_TI_J721E_R5

soc/arm/ti_k3/j721e/Kconfig.defconfig.series

@@ -0,0 +1,47 @@
+# Copyright (C) 2023 BeagleBoard.org Foundation
+# Copyright (C) 2023 S Prashanth
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if SOC_SERIES_TI_J721E
+
+source "soc/arm/ti_k3/j721e/Kconfig.defconfig.j721e*"
+
+config SOC_SERIES
+	default "j721e"
+
+config NUM_IRQS
+	default 512
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 19200000
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 10000
+
+config UART_NS16550
+	default y
+
+config UART_NS16550_TI_K3
+	default y
+
+choice UART_NS16550_VARIANT
+	default UART_NS16550_VARIANT_NS16750
+endchoice
+
+config PINCTRL
+	default y
+
+if !XIP
+	config FLASH_SIZE
+		default 0
+
+	config FLASH_BASE_ADDRESS
+		default 0
+endif # XIP
+
+# This is required for the entry point address for the elf to be zero
+config KERNEL_ENTRY
+	default "_vector_table"
+
+endif # SOC_SERIES_TI_J721E