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@silbe silbe commented Apr 27, 2023

If the boot loader already switched the system clock to PLL1 we need to switch back to HSI first and disable PLL1 before we can configure PLL1. Otherwise the register writes will simply be ignored and we'll end up with an inconsistent state.

Most of the code has been recycled from clock_stm32_ll_common.c.

If the boot loader already switched the system clock to PLL1 we need
to switch back to HSI first and disable PLL1 before we can configure
PLL1. Otherwise the register writes will simply be ignored and we'll
end up with an inconsistent state.

Most of the code has been recycled from `clock_stm32_ll_common.c`.

Signed-off-by: Sascha Silbe <[email protected]>
Signed-off-by: Sascha Silbe <[email protected]>
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Hello @silbe, and thank you very much for your first pull request to the Zephyr project!

A project maintainer just triggered our CI pipeline to run it against your PR and ensure it's compliant and doesn't cause any issues. You might want to take this opportunity to review the project's Contributor Expectations and make any updates to your pull request if necessary. 😊

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LGTM! Thanks

@carlescufi carlescufi merged commit 7628bd9 into zephyrproject-rtos:main Apr 28, 2023
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silbe commented May 2, 2023

Thanks for review & merge!

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6 participants