zephyrproject-rtos · carlescufi · Dec 22, 2022 · Dec 10, 2022 · Aug 6, 2022 · Dec 8, 2022
diff --git a/boards/arm/gd32e103v_eval/gd32e103v_eval.yaml b/boards/arm/gd32e103v_eval/gd32e103v_eval.yaml
@@ -14,3 +14,4 @@ toolchain:
 supported:
   - counter
   - watchdog
+  - dma
diff --git a/boards/arm/gd32e507v_start/gd32e507v_start.yaml b/boards/arm/gd32e507v_start/gd32e507v_start.yaml
@@ -16,3 +16,4 @@ supported:
   - gpio
   - watchdog
   - counter
+  - dma
diff --git a/boards/arm/gd32f350r_eval/gd32f350r_eval.yaml b/boards/arm/gd32f350r_eval/gd32f350r_eval.yaml
@@ -13,3 +13,4 @@ toolchain:
   - xtools
 supported:
   - watchdog
+  - dma
diff --git a/boards/arm/gd32f403z_eval/gd32f403z_eval.yaml b/boards/arm/gd32f403z_eval/gd32f403z_eval.yaml
@@ -15,3 +15,4 @@ supported:
   - counter
   - pwm
   - watchdog
+  - dma
diff --git a/boards/arm/gd32f407v_start/gd32f407v_start.yaml b/boards/arm/gd32f407v_start/gd32f407v_start.yaml
@@ -15,3 +15,4 @@ supported:
   - pwm
   - gpio
   - counter
+  - dma
diff --git a/boards/arm/gd32f450i_eval/gd32f450i_eval.yaml b/boards/arm/gd32f450i_eval/gd32f450i_eval.yaml
@@ -15,3 +15,4 @@ supported:
   - pwm
   - watchdog
   - counter
+  - dma
diff --git a/boards/arm/gd32f450v_start/gd32f450v_start.yaml b/boards/arm/gd32f450v_start/gd32f450v_start.yaml
@@ -15,3 +15,4 @@ supported:
   - pwm
   - gpio
   - counter
+  - dma
diff --git a/boards/arm/gd32f450z_eval/gd32f450z_eval.yaml b/boards/arm/gd32f450z_eval/gd32f450z_eval.yaml
@@ -20,3 +20,4 @@ supported:
   - spi
   - uart
   - watchdog
+  - dma
diff --git a/boards/arm/gd32f470i_eval/gd32f470i_eval.yaml b/boards/arm/gd32f470i_eval/gd32f470i_eval.yaml
@@ -20,3 +20,4 @@ supported:
   - spi
   - uart
   - watchdog
+  - dma
diff --git a/boards/riscv/gd32vf103c_starter/gd32vf103c_starter.yaml b/boards/riscv/gd32vf103c_starter/gd32vf103c_starter.yaml
@@ -14,3 +14,4 @@ supported:
   - gpio
   - pwm
   - watchdog
+  - dma
diff --git a/boards/riscv/gd32vf103v_eval/gd32vf103v_eval.yaml b/boards/riscv/gd32vf103v_eval/gd32vf103v_eval.yaml
@@ -14,3 +14,4 @@ supported:
   - gpio
   - pwm
   - watchdog
+  - dma
diff --git a/boards/riscv/longan_nano/longan_nano.yaml b/boards/riscv/longan_nano/longan_nano.yaml
@@ -9,3 +9,4 @@ flash: 128
 ram: 32
 supported:
   - watchdog
+  - dma
diff --git a/boards/riscv/longan_nano/longan_nano_lite.yaml b/boards/riscv/longan_nano/longan_nano_lite.yaml
@@ -9,3 +9,4 @@ flash: 64
 ram: 20
 supported:
   - watchdog
+  - dma
diff --git a/drivers/dma/Kconfig.gd32 b/drivers/dma/Kconfig.gd32
@@ -4,7 +4,7 @@
 config DMA_GD32
 	bool "Gigadevice GD32 DMA driver"
 	default y
-	depends on DT_HAS_GD_GD32_DMA_ENABLED
+	depends on DT_HAS_GD_GD32_DMA_ENABLED || DT_HAS_GD_GD32_DMA_V1_ENABLED
 	select USE_GD32_DMA
 	help
 	  DMA driver for GigaDevice GD32 series MCUs.
diff --git a/drivers/dma/dma_gd32.c b/drivers/dma/dma_gd32.c
@@ -4,8 +4,6 @@
  * SPDX-License-Identifier: Apache-2.0
  */
 
-#define DT_DRV_COMPAT gd_gd32_dma
-
 #include <zephyr/device.h>
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/drivers/clock_control/gd32.h>
@@ -16,7 +14,13 @@
 #include <gd32_dma.h>
 #include <zephyr/irq.h>
 
-#ifdef CONFIG_SOC_SERIES_GD32F4XX
+#if DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1)
+#define DT_DRV_COMPAT gd_gd32_dma_v1
+#elif DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma)
+#define DT_DRV_COMPAT gd_gd32_dma
+#endif
+
+#if DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1)
 #define CHXCTL_PERIEN_OFFSET	  ((uint32_t)25U)
 #define GD32_DMA_CHXCTL_DIR	  BIT(6)
 #define GD32_DMA_CHXCTL_M2M	  BIT(7)
@@ -58,7 +62,8 @@ struct dma_gd32_config {
 	uint32_t reg;
 	uint32_t channels;
 	uint16_t clkid;
-#ifdef CONFIG_SOC_SERIES_GD32F4XX
+	bool mem2mem;
+#if DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1)
 	struct reset_dt_spec reset;
 #endif
 	void (*irq_configure)(void);
@@ -189,7 +194,7 @@ gd32_dma_periph_width_config(uint32_t reg, dma_channel_enum ch, uint32_t pwidth)
 	GD32_DMA_CHCTL(reg, ch) = (ctl & (~DMA_CHXCTL_PWIDTH)) | pwidth;
 }
 
-#ifdef CONFIG_SOC_SERIES_GD32F4XX
+#if DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1)
 static inline void
 gd32_dma_channel_subperipheral_select(uint32_t reg, dma_channel_enum ch,
 				      dma_subperipheral_enum sub_periph)
@@ -211,7 +216,7 @@ gd32_dma_periph_address_config(uint32_t reg, dma_channel_enum ch, uint32_t addr)
 static inline void
 gd32_dma_memory_address_config(uint32_t reg, dma_channel_enum ch, uint32_t addr)
 {
-#ifdef CONFIG_SOC_SERIES_GD32F4XX
+#if DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1)
 	DMA_CHM0ADDR(reg, ch) = addr;
 #else
 	GD32_DMA_CHMADDR(reg, ch) = addr;
@@ -233,7 +238,7 @@ gd32_dma_transfer_number_get(uint32_t reg, dma_channel_enum ch)
 static inline void
 gd32_dma_interrupt_flag_clear(uint32_t reg, dma_channel_enum ch, uint32_t flag)
 {
-#ifdef CONFIG_SOC_SERIES_GD32F4XX
+#if DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1)
 	if (ch < DMA_CH4) {
 		DMA_INTC0(reg) |= DMA_FLAG_ADD(flag, ch);
 	} else {
@@ -247,7 +252,7 @@ gd32_dma_interrupt_flag_clear(uint32_t reg, dma_channel_enum ch, uint32_t flag)
 static inline void
 gd32_dma_flag_clear(uint32_t reg, dma_channel_enum ch, uint32_t flag)
 {
-#ifdef CONFIG_SOC_SERIES_GD32F4XX
+#if DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1)
 	if (ch < DMA_CH4) {
 		DMA_INTC0(reg) |= DMA_FLAG_ADD(flag, ch);
 	} else {
@@ -261,7 +266,7 @@ gd32_dma_flag_clear(uint32_t reg, dma_channel_enum ch, uint32_t flag)
 static inline uint32_t
 gd32_dma_interrupt_flag_get(uint32_t reg, dma_channel_enum ch, uint32_t flag)
 {
-#ifdef CONFIG_SOC_SERIES_GD32F4XX
+#if DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1)
 	if (ch < DMA_CH4) {
 		return (DMA_INTF0(reg) & DMA_FLAG_ADD(flag, ch));
 	} else {
@@ -279,7 +284,7 @@ static inline void gd32_dma_deinit(uint32_t reg, dma_channel_enum ch)
 	GD32_DMA_CHCTL(reg, ch) = DMA_CHCTL_RESET_VALUE;
 	GD32_DMA_CHCNT(reg, ch) = DMA_CHCNT_RESET_VALUE;
 	GD32_DMA_CHPADDR(reg, ch) = DMA_CHPADDR_RESET_VALUE;
-#ifdef CONFIG_SOC_SERIES_GD32F4XX
+#if DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1)
 	DMA_CHM0ADDR(reg, ch) = DMA_CHMADDR_RESET_VALUE;
 	DMA_CHFCTL(reg, ch) = DMA_CHFCTL_RESET_VALUE;
 	if (ch < DMA_CH4) {
@@ -403,10 +408,15 @@ static int dma_gd32_config(const struct device *dev, uint32_t channel,
 		return -ENOTSUP;
 	}
 
-#ifdef CONFIG_SOC_SERIES_GD32F4XX
-	if (dma_cfg->linked_channel > 0xF) {
-		LOG_ERR("linked_channel must be <7 (%" PRIu32 ")",
-			dma_cfg->linked_channel);
+	if (dma_cfg->channel_direction == MEMORY_TO_MEMORY && !cfg->mem2mem) {
+		LOG_ERR("not supporting MEMORY_TO_MEMORY");
+		return -ENOTSUP;
+	}
+
+#if DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1)
+	if (dma_cfg->dma_slot > 0xF) {
+		LOG_ERR("dma_slot must be <7 (%" PRIu32 ")",
+			dma_cfg->dma_slot);
 		return -EINVAL;
 	}
 #endif
@@ -462,10 +472,10 @@ static int dma_gd32_config(const struct device *dev, uint32_t channel,
 	gd32_dma_periph_width_config(cfg->reg, channel,
 				     dma_gd32_periph_width(periph_cfg->width));
 	gd32_dma_circulation_disable(cfg->reg, channel);
-#ifdef CONFIG_SOC_SERIES_GD32F4XX
+#if DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1)
 	if (dma_cfg->channel_direction != MEMORY_TO_MEMORY) {
 		gd32_dma_channel_subperipheral_select(cfg->reg, channel,
-						      dma_cfg->linked_channel);
+						      dma_cfg->dma_slot);
 	}
 #endif
 
@@ -594,7 +604,7 @@ static int dma_gd32_init(const struct device *dev)
 	(void)clock_control_on(GD32_CLOCK_CONTROLLER,
 			       (clock_control_subsys_t *)&cfg->clkid);
 
-#ifdef CONFIG_SOC_SERIES_GD32F4XX
+#if DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1)
 	(void)reset_line_toggle_dt(&cfg->reset);
 #endif
 
@@ -665,10 +675,11 @@ static const struct dma_driver_api dma_gd32_driver_api = {
 	}                                                                      \
 	static const struct dma_gd32_config dma_gd32##inst##_config = {        \
 		.reg = DT_INST_REG_ADDR(inst),                                 \
+		.channels = DT_INST_PROP(inst, dma_channels),                  \
 		.clkid = DT_INST_CLOCKS_CELL(inst, id),                        \
-		IF_ENABLED(CONFIG_SOC_SERIES_GD32F4XX,                         \
+		.mem2mem = DT_INST_PROP(inst, gd_mem2mem),                     \
+		IF_ENABLED(DT_HAS_COMPAT_STATUS_OKAY(gd_gd32_dma_v1),          \
 			   (.reset = RESET_DT_SPEC_INST_GET(inst),))           \
-		.channels = DT_INST_PROP(inst, dma_channels),                  \
 		.irq_configure = dma_gd32##inst##_irq_configure,               \
 	};                                                                     \
                                                                                \

diff --git a/dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi b/dts/arm/gigadevice/gd32e10x/gd32e10x.dtsi
@@ -472,7 +472,7 @@
 				     <15 0>, <16 0>, <17 0>;
 			clocks = <&cctl GD32_CLOCK_DMA0>;
 			dma-channels = <7>;
-			#dma-cells = <1>;
+			#dma-cells = <2>;
 			status = "disabled";
 		};
 
@@ -483,7 +483,7 @@
 				     <60 0>;
 			clocks = <&cctl GD32_CLOCK_DMA1>;
 			dma-channels = <5>;
-			#dma-cells = <1>;
+			#dma-cells = <2>;
 			status = "disabled";
 		};
 

diff --git a/dts/arm/gigadevice/gd32e50x/gd32e50x.dtsi b/dts/arm/gigadevice/gd32e50x/gd32e50x.dtsi
@@ -411,7 +411,8 @@
 				     <15 0>, <16 0>, <17 0>;
 			clocks = <&cctl GD32_CLOCK_DMA0>;
 			dma-channels = <7>;
-			#dma-cells = <1>;
+			gd,mem2mem;
+			#dma-cells = <2>;
 			status = "disabled";
 		};
 
@@ -422,7 +423,8 @@
 				     <60 0>;
 			clocks = <&cctl GD32_CLOCK_DMA1>;
 			dma-channels = <5>;
-			#dma-cells = <1>;
+			gd,mem2mem;
+			#dma-cells = <2>;
 			status = "disabled";
 		};
 	};

diff --git a/dts/arm/gigadevice/gd32f3x0/gd32f3x0.dtsi b/dts/arm/gigadevice/gd32f3x0/gd32f3x0.dtsi
@@ -97,7 +97,7 @@
 			interrupts = <9 0>, <10 0>, <11 0>, <48 0>;
 			clocks = <&cctl GD32_CLOCK_DMA>;
 			dma-channels = <7>;
-			#dma-cells = <1>;
+			#dma-cells = <2>;
 			status = "disabled";
 		};
 

diff --git a/dts/arm/gigadevice/gd32f403/gd32f403.dtsi b/dts/arm/gigadevice/gd32f403/gd32f403.dtsi
@@ -496,7 +496,8 @@
 				     <15 0>, <16 0>, <17 0>;
 			clocks = <&cctl GD32_CLOCK_DMA0>;
 			dma-channels = <7>;
-			#dma-cells = <1>;
+			gd,mem2mem;
+			#dma-cells = <2>;
 			status = "disabled";
 		};
 
@@ -507,7 +508,8 @@
 				     <60 0>;
 			clocks = <&cctl GD32_CLOCK_DMA1>;
 			dma-channels = <5>;
-			#dma-cells = <1>;
+			gd,mem2mem;
+			#dma-cells = <2>;
 			status = "disabled";
 		};
 	};

diff --git a/dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi b/dts/arm/gigadevice/gd32f4xx/gd32f4xx.dtsi
@@ -618,26 +618,28 @@
 		};
 
 		dma0: dma@40026000 {
-			compatible = "gd,gd32-dma";
+			compatible = "gd,gd32-dma-v1";
 			reg = <0x40026000 0x400>;
 			interrupts = <11 0>, <12 0>, <13 0>, <14 0>,
 				     <15 0>, <16 0>, <17 0>, <47 0>;
 			clocks = <&cctl GD32_CLOCK_DMA0>;
 			resets = <&rctl GD32_RESET_DMA0>;
 			dma-channels = <8>;
-			#dma-cells = <1>;
+			gd,mem2mem;
+			#dma-cells = <4>;
 			status = "disabled";
 		};
 
 		dma1: dma@40026400 {
-			compatible = "gd,gd32-dma";
+			compatible = "gd,gd32-dma-v1";
 			reg = <0x40026400 0x400>;
 			interrupts = <56 0>, <57 0>, <58 0>, <59 0>,
 				     <60 0>, <68 0>, <69 0>, <70 0>;
 			clocks = <&cctl GD32_CLOCK_DMA1>;
 			resets = <&rctl GD32_RESET_DMA1>;
 			dma-channels = <8>;
-			#dma-cells = <1>;
+			gd,mem2mem;
+			#dma-cells = <4>;
 			status = "disabled";
 		};
 	};

diff --git a/dts/bindings/dma/gd,gd32-dma-base.yaml b/dts/bindings/dma/gd,gd32-dma-base.yaml
@@ -0,0 +1,21 @@
+# Copyright (c) 2022, TOKITA Hiroshi <[email protected]>
+# SPDX-License-Identifier: Apache-2.0
+
+include: dma-controller.yaml
+
+properties:
+  reg:
+    required: true
+
+  interrupts:
+    required: true
+
+  dma-channels:
+    required: true
+
+  clocks:
+    required: true
+
+  gd,mem2mem:
+    type: boolean
+    description: The DMA controller supporting memory to memory transfer
-Original file line number
+Diff line change
@@ Expand Up / @@ -14,3 +14,4 @@ toolchain: @@
     supported:
       - counter
       - watchdog
+      - dma