Pin control support for i.MX application cores #45126
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danieldegrasse
requested review from
Mani-Sadhasivam,
MaureenHelm,
dleach02,
galak,
gmarull,
mmahadevan108,
mnkp and
nashif
as code owners
zephyrbot
added
manifest
west
manifest-hal_nxp
DNM
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The following west manifest projects have been modified in this Pull Request:
Note: This message is automatically posted and updated by the Manifest GitHub Action. |
29 tasks
zephyrbot
added
area: UART
zephyrbot
requested review from
anangl,
carlocaione,
dcpleung,
henrikbrixandersen,
mbolivar-nordic and
npitre
and removed request for
dleach02
Refactor iMX RT pin control support to use more generic names, as the IOMUXC peripheral is present on non RT iMX application cores. Additionally, make selection of the pin control driver occur at the SOC level. Signed-off-by: Daniel DeGrasse <[email protected]>
Add pin control group definitions for all iMX application cores. This commit does not enable pin control for any iMX cores, as the SOC level support is not present, but does define the require pin mux settings for all boards. Signed-off-by: Daniel DeGrasse <[email protected]>
Add pin control support for mcimx6x. The IOMUXC peripheral present on this SOC is identical to the one used on the iMX RT10xx series, so the dts bindings are reused. Signed-off-by: Daniel DeGrasse <[email protected]>
Add pin control support for mcimx7_m4 SOC. This reuses the existing pin control driver for the IOMUXC peripheral, but uses a new header and compatible binding to handle the different register layout on this SOC. Signed-off-by: Daniel DeGrasse <[email protected]>
Add pin control support for IOMUXC peripheral present on mimx8mq6_m4 soc. This reuses the existing pin control driver for the IOMUXC peripheral, but uses a new header and compatible binding to handle the different register layout on this SOC. Signed-off-by: Daniel DeGrasse <[email protected]>
Add pin control support for mimx8mm6_m4 IOMUXC peripheral. Signed-off-by: Daniel DeGrasse <[email protected]>
Add pin control support for IOMUXC peripheral present on mimx8ml8_m7 soc. This reuses the existing pin control driver for the IOMUXC peripheral, but uses a new header and compatible binding to handle the different register layout on this SOC. Signed-off-by: Daniel DeGrasse <[email protected]>
Add additional pin controller settings for iMX application core SOCs, as well as a "fallback" pin control setting. Signed-off-by: Daniel DeGrasse <[email protected]>
Add pin control support to gpio_imx driver, so that GPIO pin muxes will be selected when the use configures a pin as GPIO. Signed-off-by: Daniel DeGrasse <[email protected]>
Add pin control support to mcux_iuart driver. Signed-off-by: Daniel DeGrasse <[email protected]>
Add pin control support to uart_imx serial driver. Signed-off-by: Daniel DeGrasse <[email protected]>
Add pin control support to i2c_imx driver. Signed-off-by: Daniel DeGrasse <[email protected]>
Add pin control support to pwm_imx driver. Signed-off-by: Daniel DeGrasse <[email protected]>
Enable pin control on 96b_meerkbat96 board. Signed-off-by: Daniel DeGrasse <[email protected]>
Enable pin control on colibri_imx7d_m4 board. Signed-off-by: Daniel DeGrasse <[email protected]>
Enable pin control on warp7_m4 board. Signed-off-by: Daniel DeGrasse <[email protected]>
Add pin control support for udoo_neo_full_m4 board. Signed-off-by: Daniel DeGrasse <[email protected]>
Enable pin control for mimx8mm_evk board. Signed-off-by: Daniel DeGrasse <[email protected]>
Enable pin control for mimx8mp_evk board Signed-off-by: Daniel DeGrasse <[email protected]>
Enable pin control for mimx8mq_evk board. Signed-off-by: Daniel DeGrasse <[email protected]>
enable pin control for pico_pi_m4 board. Signed-off-by: Daniel DeGrasse <[email protected]>
Add initial pin control support for the A53 core of the imx8mm. Since the UART console driver is not currently enabled for this platform, there is no way to test the full pin control enablement. Therefore, CONFIG_PINCTRL is still not selected for this platform, although the required DTS definitions and pin control headers are present. Signed-off-by: Daniel DeGrasse <[email protected]>
Add partial pin control support for the imx8mp. Since the UART driver is not currently enabled, pin control cannot be tested on this platform. Therefore, only the DTS definitions required to set the pinmux options are present for this platform, and are not being applied (since CONFIG_PINCTRL=n). Signed-off-by: Daniel DeGrasse <[email protected]>
Member
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@Mani-Sadhasivam, @diegosueiro, @trowbridgec-laird, @jorisoffouga, @stanislav-poboril Please provide a review of this PR on the respective boards you have added to Zephyr Project |
dleach02
approved these changes
May 12, 2022
| IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07 = 0; | ||
| /* GPIO1_IO07 Mux Config */ | ||
| IOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO1_IO07 = 0; | ||
| IOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO1_IO07 = 0; |
Contributor
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How should these GPIO's be handled in the pinctrl dts files?
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The GPIO driver should handle these settings. Since these MUX selections are all selecting the GPIO mode for these pins, the device driver or application using these GPIO pins should call gpio_pin_configure, which will apply these pinmux settings. So these pinmux settings will not longer be applied at boot, but on an as needed basis by calls to gpio_pin_configure
mmahadevan108
approved these changes
May 12, 2022
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Pin control support for i.MX application cores, using the IOMUXC pin control driver present for i.MX RT four digit SOCs.
Board support is enabled in individual commits once SOC support is present, to improve traceability.
Note: Only the
mimx8mq_evkenablement has been tested on hardware (the rest have been verified to build). Since I don't have access to the remainder of the boards that this PR enables pin control support for, I've pinged each of the original contributors below. Since the project has to move to pin control for all in tree boards by 3.1, I would appreciate if anyone who has access to these boards could test the changes to verify everything is still working.96b_meerkat96@Mani-Sadhasivamcolibri_imx7d_m4@diegosueiromimx8mm_evk@Mani-Sadhasivammimx8mp_evk@trowbridgec-lairdmimx8mq_evkN/A (this board is tested)pico_pi_m4@jorisoffougaudoo_neo_full_m4@stanislav-poborilBesides these fully enabled boards, the A53 core on the
imx8mm_evkandimx8mp_evkarm64 targets (both contributed by @MrVan) have pin control definitions present but no pin control support enabled. The UART console is not enabled for these boards, and Zephyr is currently intended to run under Jailhouse. @MrVan - please correct me if this is wrong and the A53 cores do require full pin control enablement