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soc: esp32: linker script updates #43659
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Merged
nashif
merged 4 commits into
zephyrproject-rtos:main
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sylvioalves:bugfix/esp32_family_linker_cleanup
Apr 26, 2022
Merged
soc: esp32: linker script updates #43659
nashif
merged 4 commits into
zephyrproject-rtos:main
from
sylvioalves:bugfix/esp32_family_linker_cleanup
Apr 26, 2022
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sylvioalves
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Mar 10, 2022
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Removed snippets commit from this PR to #43725. |
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dcpleung
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Mar 15, 2022
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sylvioalves
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@dcpleung Added your suggestion/PR. |
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LGTM |
uLipe
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Apr 13, 2022
glaubermaroto
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Rebased to add latest BT_IAS config. |
mbolivar-nordic
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This looks reasonable to me.
glaubermaroto
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Apr 21, 2022
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Needs rebase |
This splits common-rom.ld into smaller snippets so that these chunks can be placed at different locations if so desired. Signed-off-by: Daniel Leung <[email protected]>
This PR removes common-rom.ld section so that logging sections can now be mapped into RAM area. Signed-off-by: Sylvio Alves <[email protected]>
This PR removes common-rom.ld section so that logging sections can now be mapped into RAM area. Signed-off-by: Sylvio Alves <[email protected]>
This PR removes common-rom.ld section so that logging sections can now be mapped into RAM area. Signed-off-by: Sylvio Alves <[email protected]>
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Rebased and re-organized |
glaubermaroto
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Apr 26, 2022
dcpleung
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Apr 26, 2022
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Labels
area: API
Changes to public APIs
area: Logging
area: RISCV
RISCV Architecture (32-bit & 64-bit)
platform: ESP32
Espressif ESP32
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This PR splits
common-rom.ldinto smaller linker files to enable custom placement of sections. It also updates ESP32 family to make use of this approach.This is useful for architectures as such as ESP32 that requires log strings to be placed in RAM area
due to flash cache access. It can also be useful for applications that have small ROM footprint.