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Atmel SAM already uses pinctrl feature but SAM0 doesn't have support. This refactor pinmux driver to use a new common SoC gpio methods. It add the gpio and pinctrl devicetree bindings structures and macros.

As part of this PR sercom[uart] driver was enhanced to use pinctrl. All sercom[uart] configuration for sam0 boards were updated to use pinctrl and pinmux entries were removed. Some samples were altered to allow consistency.

Tested with SAMR21.

@nandojve nandojve added the platform: Microchip SAM Microchip SAM Platform (formerly Atmel SAM) label May 18, 2021
@nandojve nandojve added this to the v2.7.0 milestone May 18, 2021
@nandojve nandojve requested a review from mnkp May 18, 2021 23:01
@nandojve nandojve force-pushed the sam0_pinctrl_plus_uart branch from 6331721 to ebd12fb Compare May 19, 2021 01:24
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The compliance check didn't detect some Macro construction. It is a well know problem.

@nandojve nandojve marked this pull request as ready for review May 19, 2021 15:01
@nandojve nandojve force-pushed the sam0_pinctrl_plus_uart branch from ebd12fb to 3820e76 Compare June 9, 2021 21:56
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nandojve commented Jun 9, 2021

rebase

@nandojve nandojve force-pushed the sam0_pinctrl_plus_uart branch from 3820e76 to 849a19e Compare June 20, 2021 17:34
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Hi @mnkp ,

I made apply some changes as requested. I implement a variable length macro to explicit assign pin to an peripheral. It allows add any other GPIO flag. It only add flexibility at pin definition.

@nandojve nandojve requested a review from mnkp June 20, 2021 17:49
@nandojve nandojve force-pushed the sam0_pinctrl_plus_uart branch from 849a19e to 27c15ba Compare June 22, 2021 22:07
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Looks good. So, should we change soc_gpio.c to soc_port.c and change the prefix of the functions in the file?

@nandojve nandojve force-pushed the sam0_pinctrl_plus_uart branch from 27c15ba to 2c674c8 Compare June 23, 2021 20:37
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mnkp commented Jun 23, 2021

We could update commit message of the first commit. It still refers to soc_gpio functions. But that's a minor infraction.

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We could update commit message of the first commit. It still refers to soc_gpio functions. But that's a minor infraction.

Yes, this confirm that I need one week vacation heheh.

@nandojve nandojve force-pushed the sam0_pinctrl_plus_uart branch from 2c674c8 to 2d0b362 Compare June 23, 2021 22:01
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mnkp commented Jul 16, 2021

@galak The PR looks good, we could merge it, but it requires approval from one more reviewer.

@carlescufi carlescufi requested a review from gmarull July 30, 2021 11:43
@galak galak force-pushed the sam0_pinctrl_plus_uart branch from 2d0b362 to 985915a Compare July 30, 2021 16:06
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galak commented Jul 30, 2021

Rebased on main just to make sure this still passes CI.

nandojve added 3 commits July 30, 2021 13:45
Introduce soc_port common functions.  The sam0 pinmux driver was
refactored to use soc_port_pinmux_set common function.

This create the common base to implement sam0 pinctrl functions.

Signed-off-by: Gerson Fernando Budke <[email protected]>
Add Atmel sam0 MCU series pinctrl devicetree bindings and
infrastructure.

Signed-off-by: Gerson Fernando Budke <[email protected]>
Add Atmel sam0 sercom[uart] pinctrl bindings and implements pinctrl at
driver level.  It changes all sam0 boards to use new feature and remove
pinmux driver dependency for sercom[uart].  The samples that require a
binding were update to keep consistency and avoid errors.

Signed-off-by: Gerson Fernando Budke <[email protected]>
@nandojve nandojve force-pushed the sam0_pinctrl_plus_uart branch from 985915a to 7c91f46 Compare July 30, 2021 16:45
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Rebased on main just to make sure this still passes CI.

Sure, thank you Kumar!

@galak galak merged commit 62ba472 into zephyrproject-rtos:main Jul 30, 2021
@nandojve nandojve deleted the sam0_pinctrl_plus_uart branch July 30, 2021 20:06
@nandojve nandojve mentioned this pull request Dec 15, 2021
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3 participants