Skip to content

arm: soc: nxp k6x: MPU: add Bus Master 3 User Mode access bits #261

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 2 commits into from
May 24, 2017
Merged

arm: soc: nxp k6x: MPU: add Bus Master 3 User Mode access bits #261

Changes from all commits
Commits
Show all changes
2 commits
Select commit Hold shift + click to select a range
9f1bf28
arm: soc: nxp k6x: mpu: clarify magic numbers for UM/SM defines
May 23, 2017
50abc05
arm: soc: nxp k6x: mpu: add Bus Master 3 User Mode access bits
May 23, 2017
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
61 changes: 52 additions & 9 deletions include/arch/arm/cortex_m/mpu/nxp_mpu.h
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -13,27 +13,70 @@

#define NXP_MPU_REGION_NUMBER 12

/* Bus Master User Mode Access */
#define UM_READ 4
#define UM_WRITE 2
#define UM_EXEC 1

#define BM0_UM_SHIFT 0
#define BM1_UM_SHIFT 6
#define BM2_UM_SHIFT 12
#define BM3_UM_SHIFT 18

/* Bus Master Supervisor Mode Access */
#define SM_RWX_ALLOW 0
#define SM_RX_ALLOW 1
#define SM_RW_ALLOW 2
#define SM_SAME_AS_UM 3

#define BM0_SM_SHIFT 3
#define BM1_SM_SHIFT 9
#define BM2_SM_SHIFT 15
#define BM3_SM_SHIFT 21

/* Read Attribute */
#define MPU_REGION_READ ((1 << 2) | (1 << 8) | (1 << 14))
#define MPU_REGION_READ ((UM_READ << BM0_UM_SHIFT) | \
(UM_READ << BM1_UM_SHIFT) | \
(UM_READ << BM2_UM_SHIFT) | \
(UM_READ << BM3_UM_SHIFT))

/* Write Attribute */
#define MPU_REGION_WRITE ((1 << 1) | (1 << 7) | (1 << 13))
#define MPU_REGION_WRITE ((UM_WRITE << BM0_UM_SHIFT) | \
(UM_WRITE << BM1_UM_SHIFT) | \
(UM_WRITE << BM2_UM_SHIFT) | \
(UM_WRITE << BM3_UM_SHIFT))

/* Execute Attribute */
#define MPU_REGION_EXEC ((1 << 0) | (1 << 6) | (1 << 12))
#define MPU_REGION_EXEC ((UM_EXEC << BM0_UM_SHIFT) | \
(UM_EXEC << BM1_UM_SHIFT) | \
(UM_EXEC << BM2_UM_SHIFT) | \
(UM_EXEC << BM3_UM_SHIFT))

/* Super User Attributes */
#define MPU_REGION_SU ((3 << 3) | (3 << 9) | (3 << 15) | (3 << 21))
#define MPU_REGION_SU ((SM_SAME_AS_UM << BM0_SM_SHIFT) | \
(SM_SAME_AS_UM << BM1_SM_SHIFT) | \
(SM_SAME_AS_UM << BM2_SM_SHIFT) | \
(SM_SAME_AS_UM << BM3_SM_SHIFT))

/* The ENDADDR field has the last 5 bit reserved and set to 1 */
#define ENDADDR_ROUND(x) (x - 0x1F)

/* Some helper defines for common regions */
#define REGION_RAM_ATTR (MPU_REGION_READ | MPU_REGION_WRITE | MPU_REGION_SU)
#define REGION_FLASH_ATTR (MPU_REGION_READ | MPU_REGION_EXEC | MPU_REGION_SU)
#define REGION_IO_ATTR (MPU_REGION_READ | MPU_REGION_WRITE | \
MPU_REGION_EXEC | MPU_REGION_SU)
#define REGION_RO_ATTR (MPU_REGION_READ | MPU_REGION_SU)
#define REGION_RAM_ATTR (MPU_REGION_READ | \
MPU_REGION_WRITE | \
MPU_REGION_SU)

#define REGION_FLASH_ATTR (MPU_REGION_READ | \
MPU_REGION_EXEC | \
MPU_REGION_SU)

#define REGION_IO_ATTR (MPU_REGION_READ | \
MPU_REGION_WRITE | \
MPU_REGION_EXEC | \
MPU_REGION_SU)

#define REGION_RO_ATTR (MPU_REGION_READ | \
MPU_REGION_SU)

/* Region definition data structure */
struct nxp_mpu_region {
Expand Down