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STM32G4x/STM32L4Rx/STM32L4Sx: Fix sys clock frequency and boost voltage for highest clock frequencies #22311

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Merged
merged 3 commits into from
Feb 26, 2020
Merged

STM32G4x/STM32L4Rx/STM32L4Sx: Fix sys clock frequency and boost voltage for highest clock frequencies #22311

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25dc398
driver: clock: stm32: boost voltage when clock exceeds 150MHz
FRASTM Feb 26, 2020
74079f8
driver: clock: stm32: boost voltage when clock exceeds 80MHz
FRASTM Feb 26, 2020
8210181
west.yml: update hal stm32g4xx and stm32l4R/stm32l4S modules
FRASTM Feb 12, 2020
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5 changes: 5 additions & 0 deletions drivers/clock_control/clock_stm32g4.c
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Expand Up @@ -29,6 +29,11 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
pllinit->PLLR = pllr(CONFIG_CLOCK_STM32_PLL_R_DIVISOR);

/* set power boost mode for sys clock greater than 150MHz */
if (sys_clock_hw_cycles_per_sec() >= MHZ(150)) {
LL_PWR_EnableRange1BoostMode();
}
}
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */

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6 changes: 6 additions & 0 deletions drivers/clock_control/clock_stm32l4_wb.c
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Expand Up @@ -30,6 +30,12 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
pllinit->PLLM = pllm(CONFIG_CLOCK_STM32_PLL_M_DIVISOR);
pllinit->PLLN = CONFIG_CLOCK_STM32_PLL_N_MULTIPLIER;
pllinit->PLLR = pllr(CONFIG_CLOCK_STM32_PLL_R_DIVISOR);
#ifdef PWR_CR5_R1MODE
/* set power boost mode for sys clock greater than 80MHz */
if (sys_clock_hw_cycles_per_sec() >= MHZ(80)) {
LL_PWR_EnableRange1BoostMode();
}
#endif /* PWR_CR5_R1MODE */
}
#endif /* CONFIG_CLOCK_STM32_SYSCLK_SRC_PLL */

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2 changes: 1 addition & 1 deletion west.yml
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Expand Up @@ -62,7 +62,7 @@ manifest:
revision: fa481784b3c49780f18d50bafe00390ccb62b2ec
path: modules/hal/st
- name: hal_stm32
revision: 94d735c2613f5d17b64b78a15f0b0191e4474eb0
revision: dee4413253623ec575bb8b58abd56f91afe903bb
path: modules/hal/stm32
- name: hal_ti
revision: b25d4b83b16e52f501f8cd360f4efb8c31ffb578
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