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Devicetree binding/description for pinmux on centralized pin func SoCs #29369

@galak

Description

@galak

This issue is to discuss ideas on a generic / template for describing pinmux/cfg information for SoCs that handle pincfg as part of the GPIO block. Examples of such SoCs are STM, NXP, etc.

In such systems typically the following information is related to a pin:

  • port (which GPIO block the pin is on - (GPIO A, GPIO B, GPIO C, PORT A, PORT B, PORT C, PIO 0, PIO 1, etc.)
  • pin (typically a 0..31) number for the pin on the port
  • function - how the pin is configured (used as GPIO, analog, I2C_SCL, etc)
  • attributes/flags - additional params of the pin (pull-up/pull-down, speed/slew-rate, etc).

some how all this information needs to be encoded in the devicetree.


Some general assumptions/references:

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