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RFCRequest For Comments: want input from the communityRequest For Comments: want input from the communityarea: Devicetreearea: Devicetree BindingPR modifies or adds a Device Tree bindingPR modifies or adds a Device Tree bindingarea: Pinmux
Description
This issue is to discuss ideas on a generic / template for describing pinmux/cfg information for SoCs that handle pincfg as part of the GPIO block. Examples of such SoCs are STM, NXP, etc.
In such systems typically the following information is related to a pin:
- port (which GPIO block the pin is on - (GPIO A, GPIO B, GPIO C, PORT A, PORT B, PORT C, PIO 0, PIO 1, etc.)
- pin (typically a 0..31) number for the pin on the port
- function - how the pin is configured (used as GPIO, analog, I2C_SCL, etc)
- attributes/flags - additional params of the pin (pull-up/pull-down, speed/slew-rate, etc).
some how all this information needs to be encoded in the devicetree.
Some general assumptions/references:
- We try and conform the basic concepts that already exist for pinctrl as part of the "upstream" linux bindings.
- We keep things simple for MCUs and avoid group concepts, and have a node per pin+func combination
- upstream pinctrl binding:
https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/tree/Bindings/pinctrl/pinctrl-bindings.txt
https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/tree/Bindings/pinctrl/pinmux-node.yaml - common pin attribute/flags binding:
https://git.kernel.org/pub/scm/linux/kernel/git/devicetree/devicetree-rebasing.git/tree/Bindings/pinctrl/pincfg-node.yaml
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RFCRequest For Comments: want input from the communityRequest For Comments: want input from the communityarea: Devicetreearea: Devicetree BindingPR modifies or adds a Device Tree bindingPR modifies or adds a Device Tree bindingarea: Pinmux