Extend qemu_cortex_r5 test coverage

[stephanosio]

At the time of writing, the qemu_cortex_r5 board based on xilinx_zynqmp SoC is only able to run very basic non-multitasking samples and tests (e.g. hello_world sample).

In order to improve test coverage on the qemu_cortex_r5 platform and facilitate CI testing of the ARM Cortex-R port, QEMU needs to be patched to provide a better emulation of the RPU of the Xilinx ZynqMP SoC; at the same time, incorrect xilinx_zynqmp SoC implementation on Zephyr needs to be fixed.

QEMU Tasks

• PATCH: arm/xlnx-zynqmp: put APUs and RPUs in separate CPU clusters
  (https://patchwork.kernel.org/patch/10717697)
• PATCH: xlnx-zynqmp: add the timers
  (https://patchwork.kernel.org/patch/10048347)
• PATCH: xlnx-zynqmp: add PL390 GIC for RPU
  (WIP)

A pull request incorporating the above patches is to be made on zephyr_rtos/qemu. As for the new patch(es), a pull request will be made on Xilinx/qemu and, hopefully, Xilinx will submit an upstream patch.

It seems the hard-coded qemu machine type -machine xlnx-zcu102 (currently being used as the default "run" environment by qemu_cortex_r5 board) is simply obsolete. Both RPU GIC and TTCs are properly mapped when emulating with -machine arm-generic-fdt using the latest zcu102-arm.dts from Xilinx/qemu-devicetrees.

• Add Xilinx QEMU (qemu-system-xilinx-aarch64) sdk-ng#138 Add arm-generic-fdt machine type support to Zephyr SDK qemu (this machine type is currently only available in Xilinx/qemu)

Zephyr Tasks

• Add sdk 0.11.0-alpha-5 ci-dockerfiles#55 Add Zephyr SDK 0.11.0-alpha-5 to the CI docker image
• boards: arm: qemu_cortex_r5: Use arm-generic-fdt machine type. #20298 Modify qemu_cortex_r5 board qemu emulation to use arm-generic-fdt machine type
• Refactor and fix xilinx_zynqmp SoC definition #20267 Fix incorrect xilinx_zynqmp dts (the current dts used by RPU is really that of APU, especially the GIC-400 mapping that only applies to APU)
• interrupt_controller: gic: Support multiple GIC versions #21508 Implement PL390 GICv1 support
• Implement tickless capability for xlnx_psttc_timer #19869 Implement tickless API for Cadence TTC system timer driver (withdrawn)

Note

• Since the current Zephyr architecture cannot support AMP of Zynq APUs and RPUs in one project, we should consider the APU and RPU to be different hardware platforms (i.e. consider renaming xilinx_zynqmp to xilinx_zynqmp_rpu; when Cortex-A support is added in the future, add xilinx_zynqmp_apu; qemu_cortex_a53 should then utilise xilinx_zynqmp_apu). -> This has been addressed in the PR Refactor and fix xilinx_zynqmp SoC definition #20267.
• Implement tickless capability for xlnx_psttc_timer #19869 was withdrawn from this issue due to the severe timing instability in the Xilinx QEMU that makes it impossible to emulate tickless mode operation.

[stephanosio]

cc @bbolen @wjliang @carlocaione @ioannisg

[stephanosio]

Sample qemu RPU boot command line using the latest dts:
qemu-system-aarch64 -machine arm-generic-fdt -nographic -dtb ~/Dev/xilinx-qemu-devicetrees/build/zcu102-arm.dtb -serial mon:stdio -device loader,file=/home/stephanos/Dev/zephyr-public/zephyr/tests/kernel/timer/timer_monotonic/build_cr5/zephyr/zephyr.elf,cpu-num=4 -device loader,addr=0xff5e023c,data=0x80008fde,data-len=4 -device loader,addr=0xff9a0000,data=0x80000218,data-len=4