soc: bflb: Enable bflb,l1c cache management for BL60x and BL70x

Enables controlling the cache of BL60x and BL70x

Signed-off-by: Camille BAUD <[email protected]>

Author: VynDragon

soc/bflb/bl60x/CMakeLists.txt

@@ -14,3 +14,4 @@ zephyr_code_relocate_ifdef(CONFIG_PINCTRL_BFLB LIBRARY drivers__pinctrl LOCATION
 zephyr_code_relocate_ifdef(CONFIG_SYSCON_BFLB_EFUSE LIBRARY drivers__syscon LOCATION ITCM NOKEEP)
 zephyr_code_relocate_ifdef(CONFIG_CLOCK_CONTROL_BOUFFALOLAB_BL60X
   LIBRARY drivers__clock_control LOCATION ITCM NOKEEP)
+zephyr_code_relocate_ifdef(CONFIG_CACHE_BFLB_L1C LIBRARY drivers__cache LOCATION ITCM NOKEEP)

soc/bflb/bl60x/Kconfig

@@ -5,9 +5,12 @@
 
 config SOC_SERIES_BL60X
 	select ATOMIC_OPERATIONS_C
+	select CACHE_MANAGEMENT
 	select CLOCK_CONTROL
 	select CODE_DATA_RELOCATION
 	select CPU_HAS_FPU
+	select CPU_HAS_ICACHE
+	select CPU_HAS_DCACHE
 	select FLOAT_HARD
 	select FPU
 	select GEN_IRQ_VECTOR_TABLE

soc/bflb/bl60x/Kconfig.defconfig

@@ -18,4 +18,8 @@ config ARCH_SW_ISR_TABLE_ALIGN
 config RISCV_MCAUSE_EXCEPTION_MASK
 	default 0x3FF
 
+choice CACHE_TYPE
+	default EXTERNAL_CACHE
+endchoice
+
 endif # SOC_SERIES_BL60X

soc/bflb/bl60x/soc.c

@@ -14,6 +14,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/irq.h>
+#include <zephyr/cache.h>
 
 #include <clic.h>
 #include <bflb_soc.h>
@@ -94,4 +95,6 @@ GLB_JTAG_SWAP_SET_POS);
 
 	/* init bor for all platform */
 	system_bor_init();
+
+	sys_cache_data_flush_and_invd_all();
 }

soc/bflb/bl70x/CMakeLists.txt

@@ -13,3 +13,4 @@ zephyr_code_relocate_ifdef(CONFIG_PINCTRL_BFLB LIBRARY drivers__pinctrl LOCATION
 zephyr_code_relocate_ifdef(CONFIG_SYSCON_BFLB_EFUSE LIBRARY drivers__syscon LOCATION ITCM NOKEEP)
 zephyr_code_relocate_ifdef(CONFIG_CLOCK_CONTROL_BOUFFALOLAB_BL70X
   LIBRARY drivers__clock_control LOCATION ITCM NOKEEP)
+zephyr_code_relocate_ifdef(CONFIG_CACHE_BFLB_L1C LIBRARY drivers__cache LOCATION ITCM NOKEEP)

soc/bflb/bl70x/Kconfig

@@ -4,9 +4,12 @@
 
 config SOC_SERIES_BL70X
 	select ATOMIC_OPERATIONS_C
+	select CACHE_MANAGEMENT
 	select CLOCK_CONTROL
 	select CODE_DATA_RELOCATION
 	select CPU_HAS_FPU
+	select CPU_HAS_ICACHE
+	select CPU_HAS_DCACHE
 	select FLOAT_HARD
 	select FPU
 	select GEN_IRQ_VECTOR_TABLE

soc/bflb/bl70x/Kconfig.defconfig

@@ -18,4 +18,8 @@ config ARCH_SW_ISR_TABLE_ALIGN
 config RISCV_MCAUSE_EXCEPTION_MASK
 	default 0x3FF
 
+choice CACHE_TYPE
+	default EXTERNAL_CACHE
+endchoice
+
 endif # SOC_SERIES_BL70X

soc/bflb/bl70x/soc.c

@@ -13,6 +13,7 @@
 #include <zephyr/device.h>
 #include <zephyr/init.h>
 #include <zephyr/irq.h>
+#include <zephyr/cache.h>
 
 #include <clic.h>
 #include <bflb_soc.h>
@@ -78,4 +79,6 @@ void soc_early_init_hook(void)
 
 	/* init bor for all platform */
 	system_bor_init();
+
+	sys_cache_data_flush_and_invd_all();
 }