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drivers: cache: Introduce bflb L1C cache driver
Introduce Bouffalo Lab L1C cache management functions This allows invalidating instructions and data on BL60x and BL70x Signed-off-by: Camille BAUD <[email protected]>
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‎drivers/cache/CMakeLists.txt‎

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@@ -7,6 +7,7 @@ zephyr_library_property(ALLOW_EMPTY TRUE)
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zephyr_library_sources_ifdef(CONFIG_CACHE_ASPEED cache_aspeed.c)
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zephyr_library_sources_ifdef(CONFIG_CACHE_ANDES cache_andes.c)
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zephyr_library_sources_ifdef(CONFIG_CACHE_BFLB_L1C cache_bflb_l1c.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE cache_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_CACHE_NRF_CACHE cache_nrf.c)
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zephyr_library_sources_ifdef(CONFIG_CACHE_NXP_XCACHE cache_nxp_xcache.c)

‎drivers/cache/Kconfig‎

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@@ -23,5 +23,6 @@ source "drivers/cache/Kconfig.nrf"
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source "drivers/cache/Kconfig.andes"
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source "drivers/cache/Kconfig.nxp_xcache"
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source "drivers/cache/Kconfig.stm32"
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source "drivers/cache/Kconfig.bflb"
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endif # CACHE

‎drivers/cache/Kconfig.bflb‎

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# Copyright (c) 2025 MASSDRIVER EI <massdriver.space>
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# SPDX-License-Identifier: Apache-2.0
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config CACHE_BFLB_L1C
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bool "Bouffalolab L1C cache system driver"
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default y
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select CACHE_HAS_DRIVER
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depends on DT_HAS_BFLB_L1C_ENABLED
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help
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This option enables the cache driver for the Bouffalolab L1C cache system

‎drivers/cache/cache_bflb_l1c.c‎

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/*
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* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/cache.h>
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#include <zephyr/logging/log.h>
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#include <bflb_soc.h>
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#include <hbn_reg.h>
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#include <l1c_reg.h>
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#include <zephyr/drivers/clock_control/clock_control_bflb_common.h>
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#define DT_DRV_COMPAT bflb_l1c
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#define INVLD_TIMEOUT 4194304
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LOG_MODULE_REGISTER(cache_bflb_l1c, CONFIG_CACHE_LOG_LEVEL);
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struct cache_config {
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uint32_t ways_mask;
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};
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static struct cache_config cache_cfg = {
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.ways_mask = (1 << DT_INST_PROP(0, ways_disabled)) - 1,
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};
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/* L1C supports basically a single type of invalidate & flush */
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int bflb_cache_invalidate(uint32_t timeout)
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{
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uint32_t tmp;
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tmp = *((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET));
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tmp |= 1 << L1C_BYPASS_POS;
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tmp &= ~(1 << L1C_CACHEABLE_POS);
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tmp &= ~L1C_WAY_DIS_MSK;
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tmp &= ~(1 << L1C_CNT_EN_POS);
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*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
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tmp &= ~(1 << L1C_INVALID_EN_POS);
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*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
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__asm__ volatile (".rept 4 ; nop ; .endr");
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tmp |= (1 << L1C_INVALID_EN_POS);
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*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
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__asm__ volatile (".rept 4 ; nop ; .endr");
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while ((*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET))
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& L1C_INVALID_DONE_MSK) == 0 && timeout > 0) {
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clock_bflb_settle();
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clock_bflb_settle();
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timeout--;
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}
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if (!timeout) {
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return -EIO;
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}
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#ifdef SOC_SERIES_BL70X
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tmp &= ~(1 << L1C_FLUSH_EN_POS);
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*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
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__asm__ volatile (".rept 4 ; nop ; .endr");
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tmp |= (1 << L1C_FLUSH_EN_POS);
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*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
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__asm__ volatile (".rept 4 ; nop ; .endr");
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while ((*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET))
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& L1C_FLUSH_DONE_MSK) == 0 && timeout > 0) {
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clock_bflb_settle();
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clock_bflb_settle();
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timeout--;
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}
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if (!timeout) {
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return -EIO;
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}
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tmp &= ~(1 << L1C_FLUSH_EN_POS);
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*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
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#endif
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tmp = *((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET));
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tmp |= 1 << L1C_BYPASS_POS;
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*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
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tmp &= ~(1 << L1C_BYPASS_POS);
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tmp |= 1 << L1C_CNT_EN_POS;
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*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
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tmp &= ~L1C_WAY_DIS_MSK;
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tmp |= cache_cfg.ways_mask << L1C_WAY_DIS_POS;
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*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
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tmp |= 1 << L1C_CACHEABLE_POS;
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*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
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clock_bflb_settle();
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clock_bflb_settle();
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return 0;
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}
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void cache_instr_enable(void)
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{
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cache_data_enable();
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}
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void cache_data_enable(void)
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{
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uint32_t tmp;
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tmp = *((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET));
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tmp &= ~(1 << L1C_BYPASS_POS);
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tmp |= 1 << L1C_CNT_EN_POS;
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*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
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tmp &= ~L1C_WAY_DIS_MSK;
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tmp |= cache_cfg.ways_mask << L1C_WAY_DIS_POS;
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*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
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tmp |= 1 << L1C_CACHEABLE_POS;
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*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
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}
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void cache_instr_disable(void)
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{
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cache_data_disable();
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}
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void cache_data_disable(void)
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{
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uint32_t tmp;
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tmp = *((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET));
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tmp |= 1 << L1C_BYPASS_POS;
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tmp &= ~(1 << L1C_CACHEABLE_POS);
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tmp &= ~L1C_WAY_DIS_MSK;
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tmp &= ~(1 << L1C_CNT_EN_POS);
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*((volatile uint32_t *)(L1C_BASE + L1C_CONFIG_OFFSET)) = tmp;
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}
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int cache_data_invd_all(void)
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{
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return bflb_cache_invalidate(INVLD_TIMEOUT);
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}
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int cache_data_invd_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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int cache_instr_invd_all(void)
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{
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return bflb_cache_invalidate(INVLD_TIMEOUT);
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}
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int cache_instr_invd_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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int cache_data_flush_all(void)
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{
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return bflb_cache_invalidate(INVLD_TIMEOUT);
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}
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int cache_data_flush_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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int cache_data_flush_and_invd_all(void)
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{
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return bflb_cache_invalidate(INVLD_TIMEOUT);
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}
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int cache_data_flush_and_invd_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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int cache_instr_flush_all(void)
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{
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return -ENOTSUP;
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}
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int cache_instr_flush_and_invd_all(void)
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{
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return -ENOTSUP;
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}
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int cache_instr_flush_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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int cache_instr_flush_and_invd_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}

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