1313#include <zephyr/device.h>
1414#include <zephyr/init.h>
1515#include <zephyr/irq.h>
16+ #include <zephyr/drivers/cache.h>
1617
1718#include <bflb_soc.h>
1819#include <glb_reg.h>
@@ -107,29 +108,7 @@ void system_BOD_init(void)
107108 sys_write32 (tmp , HBN_BASE + HBN_BOR_CFG_OFFSET );
108109}
109110
110- static void clean_dcache (void )
111- {
112- __asm__ volatile (
113- "fence\n"
114- /* th.dcache.call*/
115- ".insn 0x10000B\n"
116- "fence\n"
117- );
118- }
119-
120- static void clean_icache (void )
121- {
122- __asm__ volatile (
123- "fence\n"
124- "fence.i\n"
125- /* th.icache.iall */
126- ".insn 0x100000B\n"
127- "fence\n"
128- "fence.i\n"
129- );
130- }
131-
132- static void enable_icache (void )
111+ void cache_instr_enable (void )
133112{
134113 uint32_t tmp ;
135114
@@ -153,7 +132,7 @@ static void enable_icache(void)
153132 );
154133}
155134
156- static void enable_dcache (void )
135+ void cache_data_enable (void )
157136{
158137 uint32_t tmp ;
159138
@@ -250,6 +229,18 @@ static void disable_interrupt_autostacking(void)
250229}
251230
252231
232+ void arch_cache_init (void )
233+ {
234+ enable_thead_isa_ext ();
235+ set_thead_enforce_aligned (false);
236+ cache_data_enable ();
237+ enable_branchpred (true);
238+ cache_instr_enable ();
239+ disable_interrupt_autostacking ();
240+ cache_data_flush_and_invd_all ();
241+ cache_instr_invd_all ();
242+ }
243+
253244void soc_early_init_hook (void )
254245{
255246 uint32_t key ;
@@ -263,18 +254,6 @@ void soc_early_init_hook(void)
263254 sys_write32 ((1 << 5 ), PDS_BASE + PDS_USB_CTL_OFFSET );
264255 sys_write32 (0 , PDS_BASE + PDS_USB_PHY_CTRL_OFFSET );
265256
266- enable_thead_isa_ext ();
267- set_thead_enforce_aligned (false);
268- enable_dcache ();
269- /* branch prediction can cause major slowdowns (250ms -> 2 seconds)
270- * in some applications
271- */
272- enable_branchpred (true);
273- enable_icache ();
274- disable_interrupt_autostacking ();
275- clean_dcache ();
276- clean_icache ();
277-
278257 /* reset uart signals */
279258 sys_write32 (0xffffffffU , GLB_BASE + GLB_UART_CFG1_OFFSET );
280259 sys_write32 (0x0000ffffU , GLB_BASE + GLB_UART_CFG2_OFFSET );
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