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drivers: cache: Introduce xtheadcmo cache driver
Introduce xtheadcmo risc-v extenstion cache management functions Signed-off-by: Camille BAUD <[email protected]>
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‎drivers/cache/CMakeLists.txt‎

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@@ -11,3 +11,4 @@ zephyr_library_sources_ifdef(CONFIG_USERSPACE cache_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_CACHE_NRF_CACHE cache_nrf.c)
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zephyr_library_sources_ifdef(CONFIG_CACHE_NXP_XCACHE cache_nxp_xcache.c)
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zephyr_library_sources_ifdef(CONFIG_CACHE_STM32 cache_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_CACHE_XTHEADCMO cache_xtheadcmo.c)

‎drivers/cache/Kconfig‎

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@@ -23,5 +23,6 @@ source "drivers/cache/Kconfig.nrf"
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source "drivers/cache/Kconfig.andes"
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source "drivers/cache/Kconfig.nxp_xcache"
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source "drivers/cache/Kconfig.stm32"
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source "drivers/cache/Kconfig.xuantie"
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endif # CACHE

‎drivers/cache/Kconfig.xuantie‎

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# Copyright (c) 2025 MASSDRIVER EI <massdriver.space>
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# SPDX-License-Identifier: Apache-2.0
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config CACHE_XTHEADCMO
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bool "Xuantie T-HEAD xtheadcmo extension cache control driver"
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default y
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select CACHE_HAS_DRIVER
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depends on DT_HAS_XUANTIE_XTHEADCMO_ENABLED
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help
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This option enables the CACHE driver for xuantie cores using the xtheadcmo extension

‎drivers/cache/cache_xtheadcmo.c‎

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/*
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* Copyright (c) 2025 MASSDRIVER EI (massdriver.space)
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/cache.h>
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#include <zephyr/logging/log.h>
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#define DT_DRV_COMPAT xuantie_xtheadcmo
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/* This driver defines a driver to access the xtheadcmo RISC-V extension's
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* cache management functionalities.
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* Some functions are defined as weak symbol to enable overwriting them with functions defined
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* for the specific core and setup of the platform it is used with, as the bits used to enable
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* and disable functionalities may be different for each implementation.
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*/
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LOG_MODULE_REGISTER(cache_xtheadcmo, CONFIG_CACHE_LOG_LEVEL);
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struct cache_config {
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uint32_t icache_line_size;
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uint32_t dcache_line_size;
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};
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static struct cache_config cache_cfg = {
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.icache_line_size = DT_INST_PROP(0, icache_line_size),
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.dcache_line_size = DT_INST_PROP(0, dcache_line_size),
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};
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void __weak cache_data_enable(void)
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{
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/* Platform specific */
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}
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void __weak cache_data_disable(void)
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{
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/* Platform specific */
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}
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void __weak cache_instr_enable(void)
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{
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/* Platform specific */
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}
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void __weak cache_instr_disable(void)
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{
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/* Platform specific */
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}
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int cache_data_invd_all(void)
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{
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__asm__ volatile (
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"fence\n"
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/* th.dcache.iall */
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".insn 0x20000B\n"
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"fence\n"
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);
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return 0;
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}
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static void cache_invalidate_dcache_line(uintptr_t address_in)
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{
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register uintptr_t address __asm__("a3") = address_in;
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__asm__ volatile (
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/* th.dcache.ipa a3*/
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".insn 0x2A6800B\n"
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:
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: "r"(address)
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);
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}
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int cache_data_invd_range(void *addr_in, size_t size)
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{
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uintptr_t addr = (uintptr_t)addr_in;
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__asm__ volatile (
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"fence\n"
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);
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for (uintptr_t i = addr; i < addr + size; i += cache_cfg.dcache_line_size) {
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cache_invalidate_dcache_line(i);
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}
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__asm__ volatile (
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"fence\n"
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);
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return 0;
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}
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int cache_instr_invd_all(void)
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{
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__asm__ volatile (
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"fence\n"
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"fence.i\n"
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/* th.icache.iall */
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".insn 0x100000B\n"
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"fence\n"
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"fence.i\n"
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);
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return 0;
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}
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static void cache_invalidate_icache_line(uintptr_t address_in)
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{
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register uintptr_t address __asm__("a3") = address_in;
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__asm__ volatile (
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/* th.icache.ipa a3*/
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".insn 0x386800B\n"
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:
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: "r"(address)
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);
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}
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int cache_instr_invd_range(void *addr_in, size_t size)
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{
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uintptr_t addr = (uintptr_t)addr_in;
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__asm__ volatile (
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"fence\n"
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"fence.i\n"
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);
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for (uintptr_t i = addr; i < addr + size; i += cache_cfg.icache_line_size) {
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cache_invalidate_icache_line(i);
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}
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__asm__ volatile (
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"fence\n"
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"fence.i\n"
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);
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return 0;
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}
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int cache_data_flush_all(void)
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{
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__asm__ volatile (
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"fence\n"
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/* th.dcache.call */
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".insn 0x10000B\n"
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"fence\n"
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);
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return 0;
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}
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static void cache_clean_dcache_line(uintptr_t address_in)
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{
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register uintptr_t address __asm__("a3") = address_in;
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__asm__ volatile (
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/* th.dcache.cpa a3*/
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".insn 0x296800B\n"
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:
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: "r"(address)
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);
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}
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int cache_data_flush_range(void *addr_in, size_t size)
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{
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uintptr_t addr = (uintptr_t)addr_in;
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__asm__ volatile (
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"fence\n"
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);
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for (uintptr_t i = addr; i < addr + size; i += cache_cfg.dcache_line_size) {
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cache_clean_dcache_line(i);
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}
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__asm__ volatile (
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"fence\n"
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);
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return 0;
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}
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int cache_data_flush_and_invd_all(void)
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{
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__asm__ volatile (
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"fence\n"
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/* th.dcache.ciall */
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".insn 0x30000B\n"
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"fence\n"
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);
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return 0;
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}
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static void cache_clean_invalidate_dcache_line(uintptr_t address_in)
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{
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register uintptr_t address __asm__("a3") = address_in;
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__asm__ volatile (
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/* th.dcache.cipa a3*/
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".insn 0x2B6800B\n"
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:
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: "r"(address)
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);
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}
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int cache_data_flush_and_invd_range(void *addr_in, size_t size)
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{
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uintptr_t addr = (uintptr_t)addr_in;
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__asm__ volatile (
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"fence\n"
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);
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for (uintptr_t i = addr; i < addr + size; i += cache_cfg.dcache_line_size) {
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cache_clean_invalidate_dcache_line(i);
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}
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__asm__ volatile (
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"fence\n"
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);
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return 0;
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}
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int cache_instr_flush_all(void)
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{
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return -ENOTSUP;
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}
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int cache_instr_flush_and_invd_all(void)
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{
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return -ENOTSUP;
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}
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int cache_instr_flush_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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int cache_instr_flush_and_invd_range(void *addr, size_t size)
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{
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ARG_UNUSED(addr);
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ARG_UNUSED(size);
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return -ENOTSUP;
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}
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void __weak arch_cache_init(void)
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{
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/* Platform specific */
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}

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