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fix(syntax): add datatype, direction, include and correct module #247

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fix(syntax): add datatype, direction, include and correct module #247

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@NicolasDerumigny NicolasDerumigny commented Oct 29, 2024 •
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  • Allows space after verilog module name
  • Set Verilog Types as syntax highliting category Type
  • Set direction (inout, input, output) as syntax highlighting category StorageClass
  • Set parameters and localparameters as syntax highlighting category StorageClass
  • Set include as syntax highlighting category Include

@NicolasDerumigny NicolasDerumigny force-pushed the master branch 7 times, most recently from e37c63b to 68c3c38 Compare October 29, 2024 14:13
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@NicolasDerumigny