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[WIP] Adding Custom RR Graph Builder to OpenFPGA #3325

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[WIP] Adding Custom RR Graph Builder to OpenFPGA #3325

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@amin1377 amin1377 commented Oct 28, 2025

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amin1377 added 30 commits October 14, 2025 12:24
@amin1377
[cli] add crr cli parameters
76d8496
@amin1377
[setup_vpr] add structs for crrOpts
a1b7cc9
@amin1377
[utils] pass CRROpts to alloc_routing_structs
8f30644
@amin1377
[place] padd crropts to relevant funcitons in placement
f18cc17
@amin1377
[vpr][types] add t_crr_opts
81b4cc1
@amin1377
[vpr][base] pass CRROpts to relevant base functions
1500928
@amin1377
[vpr][route] pass crr_opts to relevant routing functions
4bb1fbd
@amin1377
[vpr][route] pass crr_opts to build_tileable_unidir_rr_graph
3b8da60
@amin1377
[libs][external] add openXLSX
5bdab0a
@amin1377
[cli] fix default values for crr params
b9f40e6
@amin1377
[vpr][route][tileable] call crr generator if sb_maps is not empty
664ca84
@amin1377
[libs][external] add OpenXLSX to external libs cmake
3f1518b
@amin1377
[vpr][route][rr_graph] include crr_graph_edge_builder in tileable rr …
c8c964e 
…graph builder
@amin1377
[vpr][route][crr] add df processor
b196045
@amin1377
[vpr][route][crr] add init impl for crr_graph_edge_builder
9a57b25
@amin1377
[vpr][cmake] add openXLSX
7fa8969
@amin1377
[vpr][route][rr_graph] fix warnings
e7bd77e
@amin1377
[libs][external] add yaml-cpp
1d16bf3
@amin1377
[cmake] add yaml-cpp to cmake files
afe9b9c
@amin1377
[crr][switch_block_manager] add header file
2f361fd
@amin1377
[vpr][route][crr] add pattern matcher
7ea7740
@amin1377
[vpr][route][crr][switch_block_manager] add missing libs
d2b81e6
@amin1377
[vpr][route][crr] rename pattern_match to crr_pattern_matcher
6a05626
@amin1377
[vpr][route][crr] add switch block mng impl
7343fce
@amin1377
[vpr][route][crr] add crr.h/cpp
7c03721
@amin1377
[vpr][route][crr] add crr_common.h
835f5e2
@amin1377
[vpr][route][crr] add xml_handler.h/cpp
d2619f8
@amin1377
[vpr][route][crr] fix compile problems with xml_handler
7f32380
@amin1377
[vpr][route][crr] add node_lookup_mng
d38f924
@amin1377
[vpr][route][crr] add crr thread pool
9164048
@github-actions github-actions bot added lang-perl Perl code lang-python Python code lang-shell Shell scripts (bash etc.) labels Oct 29, 2025
amin1377 added 27 commits October 29, 2025 12:27
@amin1377
[github] don't clone submodules recursively
d5a80f0
@amin1377
[libs] remove libstudxml
b62eed4
@amin1377
[lib][external][studxml] add libstudxml
2d677ca
@amin1377
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
5d5133c 
…rilog-to-routing into add_crr
@amin1377
[libs][xlnt] add cstdint
585ecaa
@amin1377
[libs][xlnt] add cstdint
e3f0f28
@amin1377
[libs][xlnt] add cstdint
61c3a21
@amin1377
[libs][xlnt] add cstdint
ca34e03
@amin1377
[vpr][route][crr] instantiate CRR vars before if block
c408a87
@amin1377
[vpr][route][crr] fix life time of crr vars
86698eb
@amin1377
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
5b17dd1 
…rilog-to-routing into add_crr
@amin1377
[vpr][route][rr_graph] make rr_node_driver_switches const in build_rr…
fe8225c 
…_graph_regular_edges
@amin1377
[vpr][route][crr] change connection's switch_id to delay_ps
3952894
@amin1377
[vpr][route][crr] set connections delay instead of switch id
16e8ffe
@amin1377
[vpr][route][crr] add find_crr_switch_id to get switch id from delay
f85d1c6
@amin1377
[vpr][route][crr] move build_edges_for_one_tileable_rr_gsb to outside…
4b438b9 
… of the if block to build IPIN/OPIN connections
@amin1377
[vpr][route][tileable] check whether track2track_map is empty
e6fc757
@amin1377
[vpr][route][crr] don't add crr connections for switch blocks on the …
e07bbd1 
…perimeter
@amin1377
[vpr][route][crr] iterate over ipin/opin ds only if their size is big…
12e17a7 
…ger than 0
@amin1377
[vpr][route][crr] remove get_preserved_edge
1ce35ad
@amin1377
[vpr][base] adding back preserve ipin/opin
11d32fa
@amin1377
[vpr][route][crr] use default ipin/opin connections based on parameters
88caeb5
@amin1377
[vpr][route][crr] fix condition to build ipin/opin connections
949e9a4
@amin1377
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
e2d0014 
…rilog-to-routing into add_crr
@amin1377
[vpr][route][crr] remove unused functions in crr_gen
a6934c2
@amin1377
[vpr][route][crr] remove thread pool
ca6fe30
@amin1377
Merge branch 'master' of https://github.com/verilog-to-routing/vtr-ve…
219ab6e 
…rilog-to-routing into add_crr
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@amin1377