[WIP] 3D OPIN-CHANZ connectivity

libs/libarchfpga/src/echo_arch.cpp

@@ -11,10 +11,6 @@
 #include "vtr_memory.h"
 #include "vtr_assert.h"
 
-/// @brief indices to lookup IPIN connection block switch name
-constexpr int ipin_cblock_switch_index_within_die = 0;
-constexpr int ipin_cblock_switch_index_between_dice = 1;
-
 void PrintArchInfo(FILE* Echo, const t_arch* arch);
 static void print_model(FILE* echo, const t_model& model);
 static void PrintPb_types_rec(FILE* Echo, const t_pb_type* pb_type, int level, const LogicalModels& models);
@@ -198,15 +194,7 @@ void PrintArchInfo(FILE* Echo, const t_arch* arch) {
             break;
     }
 
-    fprintf(Echo, "\tInput Connect Block Switch Name Within a Same Die: %s\n", arch->ipin_cblock_switch_name[ipin_cblock_switch_index_within_die].c_str());
-
-    //if there is more than one layer available, print the connection block switch name that is used for connection between two dice
-    for (const t_grid_def& layout : arch->grid_layouts) {
-        int num_layers = (int)layout.layers.size();
-        if (num_layers > 1) {
-            fprintf(Echo, "\tInput Connect Block Switch Name Between Two Dice: %s\n", arch->ipin_cblock_switch_name[ipin_cblock_switch_index_between_dice].c_str());
-        }
-    }
+    fprintf(Echo, "\tInput Connect Block Switch Name: %s\n", arch->ipin_cblock_switch_name.c_str());
 
     fprintf(Echo, "*************************************************\n\n");
     //Switch list

libs/libarchfpga/src/physical_types.h

@@ -560,7 +560,6 @@ struct t_physical_tile_type {
     int primitive_class_starting_idx = -1;
     std::unordered_map<int, t_class> primitive_class_inf; // [primitive_class_num] -> primitive_class_inf
 
-    std::vector<int> pin_layer_offset;                // [0..num_pins-1]
     std::vector<int> pin_width_offset;                // [0..num_pins-1]
     std::vector<int> pin_height_offset;               // [0..num_pins-1]
     std::vector<int> pin_class;                       // [0..num_pins-1]
@@ -1609,14 +1608,6 @@ struct t_segment_inf {
      */
     short arch_opin_switch_dec = ARCH_FPGA_UNDEFINED_VAL;
 
-    /**
-     * @brief Index of the switch type that connects output pins (OPINs) to this
-     * segment from another die (layer). Note that this index is in relation to
-     * the switches from the architecture file, not the expanded list of switches
-     * that is built at the end of build_rr_graph.
-     */
-    short arch_inter_die_switch = ARCH_FPGA_UNDEFINED_VAL;
-
     /**
      * @brief The fraction of logic blocks along its length to which this segment can connect.
      * (i.e. internal population).
@@ -2050,11 +2041,8 @@ struct t_arch {
     std::vector<t_lut_cell> lut_cells;
     std::unordered_map<std::string, std::vector<t_lut_element>> lut_elements;
 
-    // The name of the switch used for the input connection block (i.e. to
-    // connect routing tracks to block pins). tracks can be connected to
-    // ipins through the same die or from other dice, each of these
-    // types of connections requires a different switch, all names should correspond to a switch in Switches.
-    std::vector<std::string> ipin_cblock_switch_name;
+    // The name of the switch used for the input connection block (i.e. to connect routing tracks to block pins).
+    std::string ipin_cblock_switch_name;
 
     /// Set of potential device layouts
     std::vector<t_grid_def> grid_layouts;

libs/libarchfpga/src/physical_types_util.cpp

@@ -604,24 +604,6 @@ bool is_opin(int ipin, t_physical_tile_type_ptr type) {
         return false;
 }
 
-bool is_pin_conencted_to_layer(t_physical_tile_type_ptr type, int ipin, int from_layer, int to_layer, unsigned num_of_avail_layer) {
-    // if type is empty, there is no pins
-    if (type->is_empty()) {
-        return false;
-    }
-
-    // ipin should be a valid pin in physical type
-    VTR_ASSERT(ipin < type->num_pins);
-    unsigned pin_layer = from_layer + type->pin_layer_offset[ipin];
-    // if pin_offset specifies a layer that doesn't exist in arch file, we do a wrap around
-    pin_layer = (pin_layer < num_of_avail_layer) ? pin_layer : pin_layer % num_of_avail_layer;
-    if (from_layer == to_layer || int(pin_layer) == to_layer) {
-        return true;
-    }
-
-    return false;
-}
-
 std::string block_type_pin_index_to_name(t_physical_tile_type_ptr type, int pin_physical_num, bool is_flat) {
     int max_ptc = get_tile_pin_max_ptc(type, is_flat);
     VTR_ASSERT(pin_physical_num < max_ptc);

libs/libarchfpga/src/physical_types_util.h

@@ -115,9 +115,6 @@
 ///@brief Returns true if the absolute physical pin index is an output of the given physical tile type
 bool is_opin(int ipin, t_physical_tile_type_ptr type);
 
-///@brief Returns true if the specified pin is located at "from_layer" and it is connected to "to_layer"
-bool is_pin_conencted_to_layer(t_physical_tile_type_ptr type, int ipin, int from_layer, int to_layer, unsigned num_of_avail_layer);
-
 /**
  * @brief Returns the corresponding physical pin based on the input parameters:
  *

libs/libarchfpga/src/read_fpga_interchange_arch.cpp

@@ -2325,7 +2325,7 @@ struct ArchReader {
         arch_->Chans.chan_y_dist.width = 0;
         arch_->Chans.chan_y_dist.xpeak = 0;
         arch_->Chans.chan_y_dist.dc = 0;
-        arch_->ipin_cblock_switch_name.push_back(std::string("generic"));
+        arch_->ipin_cblock_switch_name = "generic";
         arch_->sb_type = e_switch_block_type::WILTON;
         arch_->Fs = 3;
         default_fc_.specified = true;