Hotfix on a corner case of tileable rr_graph direct connections #3319
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@vaughnbetz Thanks for the quick review. I will merge this PR as is and then add new testcases (generated by OpenFPGA) in a follow-up PR. |
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Description
This is to fix a corner case where the sub tile index of IPIN may not be out of range when adding direct connections.
In such case, the builder should continue, instead of keep searching and finally abort.
Related Issue
Motivation and Context
How Has This Been Tested?
Types of changes
Checklist: