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FIR-595: Update configs to add modules required for virtualization and ethernet port (non functional for dummy interface) #13

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Merged
merged 11 commits into from
Mar 14, 2025
Merged

FIR-595: Update configs to add modules required for virtualization and ethernet port (non functional for dummy interface) #13

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c3ca04b
@FIR-595: Reducded the lower UDMA reserved area to only 256 MB
Mar 7, 2025
00867dd
@FIR-595: Enabled nttables and iptables
Mar 9, 2025
0f4fd3d
@FIR-592: Moved the 128 MB reserved area to 0x60000000
Mar 9, 2025
1d16890
@FIR-595: Enable VXLAN and Wireguard
Mar 10, 2025
8ac6a7a
@FIR-595: Reverted the dtsi file
Mar 10, 2025
620b27a
@FIR-595: Removed duplicate configs
Mar 10, 2025
d78d82b
@FIR-595: Added VXLAN and UDP Tunnel support to dumy interfaces
Mar 12, 2025
04453e9
@FIR-595: Added debug prints
Mar 12, 2025
ebb42da
@FIR-595: Adding change to bring up eth0
Mar 12, 2025
2935110
@FIR-595: Reverted changes to udp_tunnel_nic.c and dummy.c
Mar 13, 2025
3bc8349
@FIR-595: Addressed review comments and minimized diffs for eth0
Mar 14, 2025
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206 changes: 206 additions & 0 deletions arch/arm64/boot/dts/intel/fm87_ftile_10g_2port_ptp.dtsi
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@@ -0,0 +1,206 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright(C) 2022, Intel Corporation
*/

/* Add this piece of dtsi fragment as #include "fm87_ftile_25g_ptp.dtsi"
* in the file socfpga_fm87_ftile_25g_ptp.dts. Compile it in the kernel along with
* socfpga_agilex.dtsi
*/

/{
soc {
agilex_hps_bridges: bus@88000000 {
compatible = "simple-bus";
reg = <0x80000000 0x60000000>,
<0xf9000000 0x00100000>;
reg-names = "axi_h2f", "axi_h2f_lw";
#address-cells = <2>;
#size-cells = <1>;
ranges = <0x00000000 0x00000000 0xf9000000 0x00001000>,
<0x00000001 0x00000000 0x80000000 0x00040000>,
<0x00000001 0x04040050 0x84040050 0x00000010>,
<0x00000001 0x04040040 0x84040040 0x00000010>;


qsfp_eth0: qsfp-eth0 {
compatible = "sff,qsfp";
i2c-bus = <&i2c0>;
qsfpdd_initmode-gpio = <&qsfpdd_ctrl_pio 1 GPIO_ACTIVE_HIGH>;
qsfpdd_modseln-gpio = <&qsfpdd_ctrl_pio 2 GPIO_ACTIVE_LOW>;
qsfpdd_modprsn-gpio = <&qsfpdd_status_pio 0 GPIO_ACTIVE_LOW>;
qsfpdd_resetn-gpio = <&qsfpdd_ctrl_pio 0 GPIO_ACTIVE_HIGH>;
qsfpdd_intn-gpio = <&qsfpdd_status_pio 1 GPIO_ACTIVE_LOW>;
agilex_hps_spim = <&qsfpdd_ctrl_pio 3 GPIO_ACTIVE_HIGH>;
maximum-power-milliwatt = <1000>;
status = "disable";
/* status = "okay"; */
};

qsfpdd_status_pio: gpio@4040050 {
compatible = "altr,pio-1.0";
reg = <0x00000001 0x04040050 0x10>;
interrupt-parent = <&intc>;
interrupts = <0 22 4>;
altr,gpio-bank-width = <4>;
altr,interrupt-type = <2>;

altr,interrupt_type = <2>;
#gpio-cells = <2>;
gpio-controller;
status = "okay";
/*status = "disable";*/
};

qsfpdd_ctrl_pio: gpio@4040040 {
compatible = "altr,pio-1.0";
reg = <0x00000001 0x04040040 0x10>;
interrupt-parent = <&intc>;
interrupts = <0 23 4>;
altr,gpio-bank-width = <4>;
altr,interrupt-type = <2>;
altr,interrupt_type = <2>;
#gpio-cells = <2>;
gpio-controller;
status = "okay";
/*status = "disable"; */
};

};
clocks {
tod_in_clock: tod_in_clock {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <156250000>;
clock-output-names = "tod_in_clock";
};
};

ptp_clockcleaner: ptp_clockcleaner {
compatible = "intel, freq-steering-zl-i2c";
dpll-name = "zl30733";
interface = "i2c";
bus-num = <1>;
bus-address = <0x70>;
};

tod_0_clk: tod_0_clk {
compatible = "intel, tod";
reg-names = "tod_ctrl",
"pps_ctrl";
reg = <0x84040000 0x00000040>,
<0x84040100 0x00000040>;
interrupt-parent = <&intc>;
interrupt-names = "pps_irq";
interrupts = <0 19 4>;
clocks = <&tod_in_clock>;
clock-names = "tod_clock";
status = "okay";
altr,has-ptp-clockcleaner;
clock-cleaner = <&ptp_clockcleaner>;
};

hssiss_0_hssiss: hssiss_0_hssiss {
compatible = "intel, hssiss-1.0";
reg-names = "sscsr";
reg = <0x88000000 0x04000000>;
reset-mode ="reg";
};
hssi_0_eth: hssi_0_eth@88000000 {
reg-names = "tx_pref" ,
"tx_csr" ,
"tx_fifo" ,
"rx_pref" ,
"rx_csr" ,
"rx_fifo" ;

reg = <0x8c480000 0x00000020>,
<0x8c480020 0x00000020>,
<0x8c480040 0x00000020>,
<0x8c480080 0x00000020>,
<0x8c4800A0 0x00000020>,
<0x8c4800C0 0x00000010>;

compatible = "altr,hssi-ftile-1.0";
tile_chan = <0x8>;
hssi_port = <0x8>;
phy-mode = "10gbase-r";
tod = <&tod_0_clk>;
hssiss = <&hssiss_0_hssiss>;
pma_type = <0x0>; // FGT - 0x00, FHT = 0x1000
altr,tx-pma-delay-ns = <0xD>;
altr,rx-pma-delay-ns = <0x8>;
altr,tx-pma-delay-fns = <0x24D>;
altr,rx-pma-delay-fns = <0x3E97>;
altr,tx-external-phy-delay-ns = <0x0>;
altr,rx-external-phy-delay-ns = <0x0>;
fec-cw-pos-rx = <0x0>;
fec-type="no-fec";
interrupt-parent = <&intc>;
interrupt-names = "tx_irq", "rx_irq";
interrupts = <0 24 4>, <0 25 4>;
qsfp-lane = <0x0>;
rx-fifo-depth = <0x4000>;
tx-fifo-depth = <0x1000>;
rx-fifo-almost-full = <0x2000>;
rx-fifo-almost-empty = <0x1000>;
altr,has-ptp;
ptp_accu_mode = "Advanced";
ptp_tx_routing_adj = <0xDE9F>; //56,991
ptp_rx_routing_adj = <0xD625>; //54,821
status = "okay";
fixed-link {
speed =<10000>;
full-duplex;
};
};
hssi_1_eth: hssi_1_eth@88000000 {
reg-names = "tx_pref" ,
"tx_csr" ,
"tx_fifo" ,
"rx_pref" ,
"rx_csr" ,
"rx_fifo" ;

reg = <0x8c4C0000 0x00000020>,
<0x8c4C0020 0x00000020>,
<0x8c4C0040 0x00000020>,
<0x8c4C0080 0x00000020>,
<0x8c4C00A0 0x00000020>,
<0x8c4C00C0 0x00000010>;

compatible = "altr,hssi-ftile-1.0";
tile_chan = <0x9>;
hssi_port = <0x9>;
phy-mode = "10gbase-r";
tod = <&tod_0_clk>;
hssiss = <&hssiss_0_hssiss>;
pma_type = <0x0>; // FGT - 0x00, FHT = 0x1000
altr,tx-pma-delay-ns = <0xD>;
altr,rx-pma-delay-ns = <0x8>;
altr,tx-pma-delay-fns = <0x24D>;
altr,rx-pma-delay-fns = <0x3E97>;
altr,tx-external-phy-delay-ns = <0x0>;
altr,rx-external-phy-delay-ns = <0x0>;
fec-cw-pos-rx = <0x0>;
fec-type="no-fec";
interrupt-parent = <&intc>;
interrupt-names = "tx_irq", "rx_irq";
interrupts = <0 26 4>, <0 27 4>;
qsfp-lane = <0x0>;
rx-fifo-depth = <0x4000>;
tx-fifo-depth = <0x1000>;
rx-fifo-almost-full = <0x2000>;
rx-fifo-almost-empty = <0x1000>;
altr,has-ptp;
ptp_accu_mode = "Advanced";
ptp_tx_routing_adj = <0xDE3C>; //56,892
ptp_rx_routing_adj = <0xD73F>; //55,103
status = "okay";
fixed-link {
speed =<10000>;
full-duplex;
};
};
};
};
4 changes: 3 additions & 1 deletion arch/arm64/boot/dts/intel/socfpga_agilex_bittware.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -4,6 +4,8 @@
*/
#include "socfpga_agilex_bittware.dtsi"
#include "socfpga_agilex_pcie_root_port.dtsi"
#include "fm87_ftile_10g_2port_ptp.dtsi"

/ {
model = "SoCFPGA Agilex BittWare";

Expand Down Expand Up @@ -48,7 +50,7 @@
};

&gmac2 {
status = "disabled";
status = "okay";
phy-mode = "rgmii";
phy-handle = <&phy0>;

Expand Down
57 changes: 57 additions & 0 deletions arch/arm64/configs/defconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -1606,3 +1606,60 @@ CONFIG_BLK_DEV_NVME=y
#CONFIG_NVME_HWMON=y
#CONFIG_NVME_FC=y
CONFIG_DUMMY=m

##########################################
# For Flannel enable config flags
# For NFT tables, STP, VXLAN and Wireguard
#########################################
CONFIG_CFS_BANDWIDTH=y
CONFIG_NETFILTER_NETLINK=m
CONFIG_NETFILTER_XT_MATCH_OWNER=m
CONFIG_NET_SCH_HFSC=m
CONFIG_NET_SCH_FQ_CODEL=m
CONFIG_NET_UDP_TUNNEL=m
CONFIG_NF_DUP_NETDEV=m
CONFIG_NF_LOG_BRIDGE=m
CONFIG_NF_TABLES_ARP=y
CONFIG_NF_TABLES_BRIDGE=y
CONFIG_NF_TABLES_INET=y
CONFIG_NF_TABLES_IPV4=y
CONFIG_NF_TABLES_IPV6=y
CONFIG_NF_TABLES=m
CONFIG_NF_TABLES_NETDEV=y
CONFIG_NFT_BRIDGE_REJECT=m
CONFIG_NFT_CHAIN_NAT_IPV4=m
CONFIG_NFT_CHAIN_ROUTE_IPV4=m
CONFIG_NFT_CHAIN_ROUTE_IPV6=m
CONFIG_NFT_COMPAT=m
CONFIG_NFT_COUNTER=m
CONFIG_NFT_CT=m
CONFIG_NFT_DUP_IPV4=m
CONFIG_NFT_DUP_IPV6=m
CONFIG_NFT_DUP_NETDEV=m
CONFIG_NFT_FIB_INET=m
CONFIG_NFT_FIB_IPV4=m
CONFIG_NFT_FIB_IPV6=m
CONFIG_NFT_FIB_NETDEV=m
CONFIG_NFT_FWD_NETDEV=m
CONFIG_NFT_HASH=m
CONFIG_NFT_LIMIT=m
CONFIG_NFT_LOG=m
CONFIG_NFT_MASQ_IPV4=m
CONFIG_NFT_MASQ=m
CONFIG_NFT_NAT=m
CONFIG_NFT_NUMGEN=m
CONFIG_NFT_QUEUE=m
CONFIG_NFT_QUOTA=m
CONFIG_NFT_REDIR_IPV4=m
CONFIG_NFT_REDIR=m
CONFIG_NFT_REJECT=m
CONFIG_NFT_REJECT_INET=m
CONFIG_NFT_REJECT_IPV4=m
CONFIG_NFT_REJECT_IPV6=m
CONFIG_NFT_CONNLIMIT=m
CONFIG_NFT_TUNNEL=m
CONFIG_NFT_OBJREF=m
CONFIG_NFT_QUEUE=m
CONFIG_STP=m
CONFIG_VXLAN=m
CONFIG_WIREGUARD=m